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MT91L61AN 参数 Datasheet PDF下载

MT91L61AN图片预览
型号: MT91L61AN
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 - CMOS 3伏多功能的编解码器( MFC) [ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)]
分类和应用: 解码器编解码器
文件页数/大小: 32 页 / 148 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT91L60/61  
When 0, D-Channel data is shifted at the rate of 2  
bits/frame (16 kb/s default).  
frame. By arbitrarily assigning ST-BUS frame n as  
the  
reference  
frame,  
during  
which  
the  
microprocessor D-Channel read and write operations  
are performed, then:  
16 kb/s D-Channel operation is the default mode  
which allows the microprocessor access to a full byte  
of D-Channel information every fourth ST-BUS  
COMMAND/ADDRESS  
DATA INPUT/OUTPUT  
COMMAND/ADDRESS:  
DATA 1  
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
RECEIVE  
D
D
D
D
D
D
D
DATA 1  
TRANSMIT  
0
1
2
3
4
5
6
7
0
1
2
3
4
5 6  
7
SCLK  
CS  
Delays due to internal processor timing which are transparent.  
The MT91L60/L61:latches received data on the rising edge of SCLK.  
-outputs transmit data on the falling edge of SCLK.  
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The  
subsequent byte is always data until terminated via CS returning high.  
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.  
D
D
0
7
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write  
3 bits - Addressing Data  
4 bits - Unused  
X
X
X
X
A
A
A
0
R/W  
2
1
Figure 4 - Serial Port Relative Timing for Intel Mode 0  
COMMAND/ADDRESS:  
COMMAND/ADDRESS  
DATA INPUT/OUTPUT  
DATA 2  
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RECEIVE  
D
D
D
D
D
D
D
DATA 1  
TRANSMIT  
7
6
5
4
3
2
1
0
7
6
5
4
3
2 1  
0
SCLK  
CS  
Delays due to internal processor timing which are transparent .  
The MT91L60/L61: latches received data on the rising edge of SCLK.  
-outputs transmit data on the falling edge of SCLK.  
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The  
subsequent byte is always data until terminated via CS returning high.  
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.  
D
D
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write  
3 bits - Addressing Data  
4 bits - Unused  
7
0
A
R/W  
X
X
X
A
A
X
2
1
0
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire  
7
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