MT91L60/61
Advance Information
MT91L60AE
MT91L61AE/AS/AN
MT91L60AS/AN
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
1
1
2
3
4
5
6
7
8
M +
M -
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
NC
STB/F0i
Din
M +
M -
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
STBd/FOod
STB/F0i
Din
2
1
2
3
4
5
6
7
8
VBias
VRef
PWRST
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
M +
M -
20
19
18
17
16
15
14
13
12
11
3
4
5
6
7
8
9
10
11
12
VSSA
HSPKR +
HSPKR -
VDD
CLOCKin
STB/F0i
Din
NC
NC
9
SCLK
DATA1
DATA2
SCLK
DATA1
DATA2
10
11
12
9
10
Dout
Dout
Dout
24 PIN PDIP
24 PIN PDIP/SOIC/SSOP
20 PIN SOIC/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20 Pin
24 Pin
1
1
VBias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1 µF capacitor to VSSA
.
2
2
VRef
Reference Voltage for Codec (Output). Used internally. Nominally [Vdd/2 - 1.1]
volts. Connect 0.1 µF capacitor to VSSA
.
3
4
5
4
5
6
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
IC Internal Connection. Tie externally to VSSD for normal operation.
A/µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs
the companding law used by the filter/Codec; µ-Law when tied to VSSD and A-Law
when tied to VDD. Logically OR’ed with A/µ register bit.
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
6
7
7
8
VSSD Digital Ground. Nominally 0 volts.
CS
Chip Select (Input). This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
8
9
10
11
SCLK Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level
compatible.
DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
10
11
12
13
DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
Dout
Data Output. A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
12
14
Din
Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
2
MITEL [ MITEL NETWORKS CORPORATION ]
