Advance Information
MT9160B/61B
AC Electrical Characteristics† - ST-BUS Timing (See figure 11)
‡
Characteristics
C4i Clock Period
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
t
244
122
122
20
ns
ns
ns
ns
ns
ns
ns
C4P
C4i Clock High period
t
C4H
C4i Clock Low period
t
C4L
C4i Clock Transition Time
F0i Frame Pulse Setup Time
F0i Frame Pulse Hold Time
t
T
t
40
40
F0iS
F0iH
t
Delayed Frame Pulse delay
after C4i rising
t
20
20
50
50
F0odS
F0odH
DSToD
8
9
Delayed Frame Pulse hold
time from C4i rising
t
ns
DSTo Delay
t
100
125
ns
ns
ns
C = 50pF, 1kΩ load.*
L
10 DSTi Setup Time
t
20
50
DSTiS
11 DSTi Hold Time
t
DSTiH
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions → data-data, data-HiZ, HiZ-data.
t
T
1 bit cell
t
T
t
t
t
C4L
C4P
C4H
70%
30%
C4i
t
DSToD
70%
30%
DSTo
DSTi
F0i
t
t
DSTiH
DSTiS
70%
30%
t
t
F0iS
F0iH
t
t
T
T
70%
30%
t
t
F0odH
F0odS
F0od
70%
30%
64 Clock Periods
NOTE: Levels refer to %V
DD
Figure 11 - ST-BUS Timing Diagram
100
MITEL [ MITEL NETWORKS CORPORATION ]
