欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT9125 参数 Datasheet PDF下载

MT9125图片预览
型号: MT9125
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS双ADPCM代码转换器 [CMOS Dual ADPCM Transcoder]
分类和应用: 转换器PC
文件页数/大小: 16 页 / 302 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
 浏览型号MT9125的Datasheet PDF文件第2页浏览型号MT9125的Datasheet PDF文件第3页浏览型号MT9125的Datasheet PDF文件第4页浏览型号MT9125的Datasheet PDF文件第5页浏览型号MT9125的Datasheet PDF文件第7页浏览型号MT9125的Datasheet PDF文件第8页浏览型号MT9125的Datasheet PDF文件第9页浏览型号MT9125的Datasheet PDF文件第10页  
MT9125
F0i
Channel 0
DSTi/o
B1
Channel 1
B2
Channel 2
B1
Preliminary Information
Channel 3
B2
EN1
EN2
ENS=0
ADPCMi/o
B1
B2
EN1
EN2
ENS=1
ADPCMi/o
In ST-BUS mode the ENA, ENB1 and ENB2 input strobes are ignored. All timing is
dervied internally from the F0i, MCLK and ENS inputs.
B1
B2
Figure 4 - ST-BUS Mode Relative Timing
the device and must, therefore, be present whenever
a transcoding operation is required. These inputs
may be tied together and connected to the same
strobe for single channel operation. Only the B1
nibble is valid in this mode. Data is latched into the
DSTi pin with the falling edge of the bit clock while
output data is made available at DSTo on the rising
edge of the bit clock.
ST-BUS Conversion (F0i, C2o, EN1, EN2, ENS)
A simple converter circuit is incorporated which
allows ST-BUS signals to be converted to SSI
signals. In this manner it is very simple for an ST-
BUS application to be mixed with CODECs utilizing a
strobed data I/O.
This converter circuit consists of the F0i input and
C2o, EN1 and EN2 output pins (as well as the MCLK
input master clock). The output C4b clock and frame
pulse strobe (F0b), from the ST-BUS layer 1
transceiver, are connected directly to the master
clock (MCLK) and frame pulse (F0i) inputs of the
transcoder. A 2.048 MHz (C2o) bit clock output is
made available when a valid Frame Pulse is
connected to the F0i pin or the F0i pin is tied high. If
the F0i pin is tied low the C2o output is forced
continuously to a logic low level (not tri-stated).
8-22
Forcing the C2o output to logic low enhances power
conservation as well as removing a non-required
clock signal from the circuit. This 2.048 MHz bit clock
may be used to control external CODEC functions.
The 4.096 MHz and frame pulse signals are also
decoded into two output strobes corresponding to
the B1 and B2 channel timeslots of the ST-BUS.
These strobes (EN1 and EN2) are then used to
control the timing inputs of an external CODEC. A
typical example of this connection scheme is shown
in the application diagram of Figure 7.
The Enable Strobe pin (ENS) is used to position the
output strobes EN1 and EN2 within the ST-BUS
frame. Referring to Figure 4, when ENS=0 the output
strobes are positioned in channels 0 and 1 of the ST-
BUS frame. When ENS=1 the output strobes are
positioned in channels 2 and 3 of the ST-BUS frame.
This flexibility allows the transcoder to be used in
ST-BUS basic rate applications where channels 0
and 1 are defined as the D and C channels,
respectively, and also in line-card applications where
the full 2.048 MHz bandwidth is used for conveying
data and/or digitally encoded voice information.