MT9125
Pin Description (continued)
Pin #
DIP
PLCC
Preliminary Information
Name
EN1
Description
Channel 1 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i
signals and its position, within the ST-BUS stream, may be controlled via the ENS pin.
Refer to the ST-BUS relative timing diagram shown in Figure 4.
Channel 2 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i
signals and its position, within the ST-BUS stream, may be controlled via the ENS pin.
Refer to the ST-BUS timing diagram shown in Figure 4.
Enable Select input for ST-BUS operation only. This control pin changes the ST-BUS
channel position of EN1 and EN2 as well as the ADPCM channel position. Refer to the ST-
BUS timing diagram shown in Figure 4. When not used this pin should be tied to V
DD
. This
is a TTL level input.
No Connection. Leave open circuit.
22
26
23
27
EN2
24
28
ENS
1, 9,
15,
21
NC
Functional Description
The Dual-channel ADPCM Transcoder is a low
power, CMOS device capable of two encoder
functions and two decoder functions. Two 64 kbit/s
PCM channels (PCM octets) are compressed into
two 32 kbit/s ADPCM channels (ADPCM words), and
two 32 kbit/s ADPCM channels (ADPCM words) are
expanded into two 64 kbit/s PCM channels (PCM
octets). The ADPCM transcoding algorithm utilized
conforms to CCITT recommendation G.721 and
ANSI T1.303-1989. The device also supports a 24
kbit/s (three bit word) algorithm (CCITT/G.723).
Switching, on-the-fly, between 32 kbit/s and 24 kbit/s
is possible by toggling the appropriate Mode Select
(MS1-MS4) control pins.
The internal circuitry requires very little power to
operate; 25mW typically for dual channel operation.
A master clock frequency of 4.096 MHz is required
for the circuit to complete two encode channels and
two decode channels. Operation with an
asynchronous master clock, relative to the 8 kHz
reference, is allowed.
All optional functions of the device are pin selected,
no microprocessor is required. This allows a simple
interface with industry standard Codecs, Dual
Codecs, Digital Phone devices, and Layer 1
transceivers.
The PCM and ADPCM serial busses are a
Synchronous Serial Interface (SSI), allowing serial
clock rates from 128 kHz to 2.048 MHz. Additional
pins on the device allow an easy interface to an ST-
BUS component. On chip channel counters provide
channel enable outputs, as well as a 2.048 MHz
8-20
clock output, useful for driving the timing input pins
of standard CODEC devices.
Serial I/O Ports (ADPCMi, ADPCMo, ENA, ENB1,
ENB2, DSTi, DSTo, C2o, EN1, EN2, ENS, F0i)
Serial I/O data transfer to the Dual ADPCM
Transcoder is provided through the PCM and the
ADPCM ports. Serial I/O port operation is similar for
both ST-BUS and SSI modes. The Dual ADPCM
Transcoder determines the mode of operation by
monitoring the signal applied to the F0i pin. When a
valid ST-BUS Frame Pulse (244ns low going pulse)
is connected to the F0i pin the transcoder will
assume ST-BUS operation. If F0i is tied continuously
to V
SS
the transcoder will assume SSI operation. Pin
functionality in each of these modes is described in
the following sub-sections.
ADPCM Port Operation (ADPCMi, ADPCMo, ENA)
The ADPCM port consists of ADPCMi, ADPCMo and
ENA. ADPCM port functionality is similar for both ST-
BUS and SSI operation, the difference being in
where the BCLK signal is derived and in where the
ADPCM words are placed within the 8 kHz frame.
For SSI operation (i.e., when F0i is tied continuously
to V
SS
) both channels of ADPCM code words are
transferred over ADPCMi/ADPCMo at the bit clock
rate (BCLK) during the channel time defined by the
input strobe at ENA. Refer to Figure 3 and to Figure
13. Data is latched into the ADPCMi pin with the
falling edge of BCLK while output data is made
available at ADPCMo on the rising edge of BCLK.
MITEL [ MITEL NETWORKS CORPORATION ]
