MT90810
Preliminary Information
AC Electrical Characteristics - DMA Timing
Characteristics
Sym
Min.
Typ.
Max. Units
Test Conditions
1
2
3
4
5
6
7
C2o low to DACK1 asserted
C2o low to DACK0 asserted
DACK1 asserted to RD low
DACK0 asserted to WR low
C2 low to DREQ1 asserted
C2 low to DREQ0 asserted
tCDAK1
tCDAK0
tDAKR
ns
ns
ns
ns
ns
ns
ns
DMA
controller
dependent
tDAKW
tCDRQ1
tCDRQ0
tRDRQ
0
0
0
30
30
30
RD low (on 4th DMA read pulse) to
DREQ1 removed
8
WR low (on 4th DMA write pulse) to
DREQ0 removed
tWDRQ
0
30
ns
9
8
RD pulse width (DMA=fast read)
WR pulse width (DMA=fast write)
tRW
100
100
ns
ns
tWW
2Mb/s timeslot (3.9µs)
F0b
C2o
Detail a
t
CDAK1
DREQ1
DACK1
RD
t
CDAK0
t
DAKR
DREQ0
DACK0
WR
t
DAKW
Note:
DMA Read and Write cycles are asynchronous to C2o.
Figure 26 - DMA Interface Timing
2-176
MITEL [ MITEL NETWORKS CORPORATION ]
