MT90863
Advance Information
Measurement Result from
Frame Delay Bits
Corresponding
Offset Bits
Input Stream
Offset
FD9
FD2
FD1
FD0
IFn2
IFn1
IFn0
DLEn
No clock period shift (Default)
+ 0.5 clock period shift
+1.0 clock period shift
+1.5 clock period shift
+2.0 clock period shift
+2.5 clock period shift
+3.0 clock period shift
+3.5 clock period shift
+4.0 clock period shift
+4.5 clock period shift
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Table 11 - Offset Bits (IFn2, IFn1, IFn0, DLEn) & Input Offset Bits (FD9, FD2-0)
ST-BUS F0i
C16i
offset=0, DLE=0
STio Stream
STio Stream
STio Stream
STio Stream
Bit 7
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
Bit 7
Bit 7
Bit 7
denotes the 3/4 point of the bit cell
Figure 9 - Examples for Input Offset Delay Timing
18
MITEL [ MITEL NETWORKS CORPORATION ]
