Advance Information
MT90863
Read/Write Address:
04 for DOS0 register,
H
05 for DOS1 register,
H
06 for DOS2 register,
H
07 for DOS3 register,
H
08 for DOS4 register,
H
09 for DOS5 register,
H
Reset value:
0000 for all DOS registers.
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF32
IF31
IF30
DLE3
IF22
IF21
IF20
DLE2
IF12
IF11
IF10
DLE1
IF02
IF01
IF00
DLE0
DOS0 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF72
IF71
IF70
DLE7
IF62
IF61
IF60
DLE6
IF52
IF51
IF50
DLE5
IF42
IF41
IF40
DLE4
DOS1 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF112 IF111 IF110 DLE11 IF102 IF101 IF100 DLE10 IF92
IF91
IF90
DLE9
IF82
IF81
IF80
DLE8
DOS2 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF152 IF151 IF150 DLE15 IF142 IF141 IF140 DLE14 IF132 IF131 IF130 DLE13 IF122 IF121 IF120 DLE12
DOS3 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF192 IF191 IF190 DLE19 IF182 IF181 IF180 DLE18 IF172 IF171 IF170 DLE17 IF162 IF161
IF160 DLE16
DOS4 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF232
IF231
IF230 DLE23 IF222
IF221
IF220 DLE22 IF212
IF211
IF210 DLE21 IF202
IF201
IF200 DLE20
DOS5 register
Name
(Note 1)
Description
IFn2, IFn1, IFn0
Input Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STio pin: i.e., to start a new frame. The input
frame offset can be selected to +4 clock periods from the point where the external frame
pulse input signal is applied to the F0i inputs of the device.
DLEn
Data Latch Edge.
ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if clock falling edge is at the 3/4 point of the bit cell.
Note 1: n denotes a STio stream number from 0 to 23.
Table 10 - Frame Delay Offset (DOS) Register Bits
17
MITEL [ MITEL NETWORKS CORPORATION ]
