MT9080AP 参数 Datasheet PDF下载

MT9080

CMOS

Œ

CK

y

P

W

P

R

Ž



External

Address

Bus A0-A15

Data Output

D0-D15o

CH X

CH Y

CH Z

CH X

CH Y

CH Z

FP

Counter Reset

Address

generated by

Internal 11

Bit Counter

Data Input

D0-D15i

1022

1023

0

1

1023

0

P = Precharge

R = Read Memory

W = Write Memory

1

2

Data is clocked out of the memory location addressed by external address bus. The address is latched in with CK edge

marked

Œ.

Data is clocked out with CK edge marked

y.

Data is latched into the device with the last rising edge of CK in the timeslot (e.g., edge

Ž

in diagram). It is stored in the

memory location address by the internal 11 bit counter with the next rising clock edge (edge



in diagram).

Figure 4 - Data Memory Mode Functional Timing

Œ

CK

P

W

y

P

R

Input

Data

1

2

3

4

Output

Timeslots

1

2

P = Precharge

R = Read Memory

W = Write Memory

3

4

5

Data on the input bus of the SMX is latched into the device with last rising edge of the clock within a timeslot. It is

written into the internal memory with the following positive edge.

Data is clocked out of the memory location and latched onto the output data bus with first positive clock edge in the

timeslot.

Switching channel 1 to channel 1 or channel 2 will result in one frame delay. Note that channel 2 is clocked out by CK

edge labelled

Œ

while channel 1 is written into the memory with edge

y.

However, if channel 1 is switched to channel

3, there will be only one channel delay.

Figure 5 - Throughput Delay in Data Memory Mode-1

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