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MT9076AP 参数 Datasheet PDF下载

MT9076AP图片预览
型号: MT9076AP
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1 3.3V单芯片收发器 [T1/E1/J1 3.3V Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 160 页 / 413 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9076
T1/J1 Mode
Preliminary Information
E1 Mode
HDLC0
• Assignable to the ESF Facility Data Link or
any channel
• Operates at 4 kbps, 56 kbps or 64 kbps
HDLC1, HDLC2
• Assignable to any channel
• Operates at 56 kbps or 64 kbps
HDLC0
• Assigned to timeslot-0, bits Sa4~Sa8 or any
other timeslot
Operates at 4, 8, 12, 16 or 20 kbps
depending on which Sa bits are selected for
HDLC0 use
HDLC1, HDLC
• Assigned to any timeslot except timeslot-0
• Operates at 64 kbps
Slip Buffers
T1/J1 Mode
E1 Mode
Transmit Slip Buffer
• Two-frame slip buffer capable of performing a
controlled slip
Intended for rate conversion and jitter
attenuation in the transmit direction
Programmable delay
Transmit slips are independent of receive
slips
Indication of slip direction
Receive Slip Buffer
• Two-frame slip buffer capable of performing a
controlled slip
Wander tolerance of 208 UI peak-to-peak
Indication of slip direction
Receive Slip Buffer
• Two-frame slip buffer capable of performing a
controlled slip
Wander tolerance of 142 UI (92
µs)
peak
Indication of slip direction
Jitter Attenuator FIFO
A jitter attenuator FIFO is available on the transmit side in E1 mode and in IMA mode. The depth of the
JA FIFO can be configured to be from16 bits deep to 128 bits deep in 16 bit increments
Inverse Mux for ATM (IMA) Mode
T1/J1 Mode
Transmit and receive datastreams are
independently timed
The transmit clock synchronizes to a
1,544MHz clock
Transmit and receive slip buffers are
bypassed
Robbed bit signaling and HDLCs are disabled
E1 Mode
Transmit and receive datastreams are
independently timed
Receive slip buffer is bypassed
CAS and HDLCs are disabled
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