MT9076
Preliminary Information
Digital Framer Mode
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The LIU can be disabled and bypassed to allow the MT9076 to be used as a digital framer
Single phase NRZ or two phase NRZ modes are software selectable
Line coding is software selectable
Phase Lock Loop
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Locks to a 4.096 MHz input clock, or to the 1.544MHz / 2.048MHz extracted clock
IMA mode locks to 1,544MHz or 2,048MHz external clock
Attenuates jitter from less than 2.5 Hz with a roll off of 20 dB/decade
Attenuates jitter in the transmit or receive direction
Intrinsic jitter less than 0.02 UI
Meets the jitter characteristics as specified in AT&T TR62411
Meets the jitter characteristics as specified in ETS 300 011
Can be operated in Free-run, Line Synchronous or System Bus Synchronous modes
Access and Control
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MT9076 registers can be accessed via an 8-bit non-multiplexed parallel microprocessor port
The parallel port can be configured for Motorola or Intel style control signals
Backplane Interfaces
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2.048Mbit/s or 8.192Mbit/s ST-BUS
IMA mode, 1.544Mbit/s (T1) or 2.048Mbit/s (E1) serial bus with asynchronous transmit and receive
timing for Inverse MUX for ATM (IMA) applications. Slip buffers are bypassed and signaling is disabled.
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CSTo/CSTi pins can be used to access the receive/transmit signaling data
RxDL pin can be used to access the entire B8ZS/HDB3 decoded receive stream including framing bits
TxDL pin can be used to transmit data on the FDL (T1) or the Sa bits (E1)
T1/J1 Mode
E1 Mode
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PCM-24 channels 1-24 are mapped to ST-
BUS channels 0-23 respectively
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PCM-30 timeslots 0-31 are mapped to ST-
BUS channels 0-31 respectively
The framing-bit is mapped to ST-BUS
channel 31
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MITEL [ MITEL NETWORKS CORPORATION ]
