Preliminary Information
MT9076
Maskable Interrupts
T1/J1 Mode
E1 Mode
HDLC Interrupts
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Change of state of terminal
synchronization
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Change of state of basic
frame alignment
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Go ahead pattern received
End of packet received
End of packet transmitted
Change of state of multiframe
synchronization
Change of state of multiframe
synchronization
End of packet read from
receive FIFO
Change of received bit
oriented message
Change of state of CRC-4
multiframe synchronization
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Transmit FIFO low
Change of state of reception
of AIS
Change of state of reception
of AIS
Frame abort received
Transmit FIFO underrun
Receive FIFO full
Change of state of reception
of LOS
Change of state of reception
of LOS
Receive FIFO overflow
Reception of a severely
errored frame
Reception of consecutively
errored FASs
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Transmit slip
Receive remote signaling
multiframe alarm
Receive slip
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Receive slip
Receive framing bit error
Receive CRC-6 error
Receive yellow alarm
Receive FAS error
Receive CRC-4 error
Receive E-bit
Change of receive frame
alignment
Receive AIS in timeslot 16
Line code violation
Receive PRBS error
Receive auxiliary pattern
Receive RAI
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Receive line code violation
Receive PRBS error
Pulse density violation
Framing bit error counter
overflow
FAS error counter overflow
CRC-4 error counter overflow
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CRC-6 error counter overflow
Out of frame alignment
counter overflow
Out of frame alignment
counter overflow
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Change of frame alignment
counter overflow
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Receive E-bit counter
overflow
Line code violation counter
overflow
Line code violation counter
overflow
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PRBS error counter overflow
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PRBS error counter overflow
PRBS multiframe counter
overflow
PRBS multiframe counter
overflow
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Multiframes out of alignment
counter overflow
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Change of state of any Sa bit
or Sa nibble
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Loop code detected
One second timer
Five second timer
Jitter attenuator within 4 bits
of overflow/underflow
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One second timer
Receive new bit oriented
message (debounced)
Two second timer
Signaling (CAS) bit change
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Signaling (AB or ABCD) bit
change
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