Preliminary Information
MT9075B
Bit
Name
Functional Description
Bit
Name
Functional Description
7 - 0 EFAS7 Errored FAS Counter. An 8 bit
7 - 0 BPV15 BPV Counter. The most significant
counter that is incremented once for
every receive frame alignment
signal that contains one or more
errors.
eight bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.
-
-
EFAS0
BPV8
Table 62 - Most Significant Bits of the BPV
Counter (Page 04H, Address 1CH)
Table 60 - Errored Frame Alignment Signal
Counter (Page 04H, Address 1AH)
Bit
Name
Functional Description
Bit
Name
Functional Description
7 - 0
BPV7 BPV Counter. The least significant
7
RAI
Remote Alarm Indication. This bit
is set to one in the event of receipt
of a remote alarm, i.e. A(RAI) = 1. It
is cleared when the register is read.
eight bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.
-
BPV0
Table 63 - Least Significant Bits of the PBV
Counter (Page 04H, Address 1DH)
6
5
AIS
Alarm Indication Signal. This bit is
set to one in the event of receipt of
an all ones alarm. It is cleared when
the register is read.
Bit
Name
Functional Description
Unused
AIS16 AIS Time Slot 16 Alarm. This bit is
set to one in the event of receipt of
an all ones alarm in the time slot 16.
It is cleared when the register is
read.
7 - 2
1 - 0
- - -
CC9-
CC8
CRC-4 Error Counter. The most
significant eight bits of the CRC-4
error counter.
4
3
2
1
0
LOS
Loss of Signal. This bit is set to
one in the event of loss of received
signal. It is cleared when the
register is read.
Table 64 - CRC-4 Error Counter
(Page 04H, Address 1EH)
AUXP Auxiliary Alarm. This bit is set to
one in the event of receipt of the
auxiliary alarm pattern. It is cleared
when the register is read.
Bit
Name
Functional Description
7 - 0
CC7-
CC0
CRC-4 Error Counter. The least
significant eight bits of the CRC-4
error counter.
MFALM Multiframe Alarm. This bit is set
to one in the event of receipt of a
multiframe alarm. It is cleared when
the register is read.
Table 65 - CRC-4 Error Counter
(Page 04H, Address 1FH)
RSLIP Received Slip. This bit is set to one
in the event of receive elastic buffer
slip. It is cleared when the register is
read.
- - -
Unused.
Table 61 - Alarm Reporting Latch
(Page 04H, Address 1BH)
51
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