MT9075B
Preliminary Information
Bit
Name
Functional Description
Bit
Name
Functional Description
7
PRBSO PRBS Error Counter Overflow.
This bit is set to one when the
PRBS Error Counter (page 04H
address 10H) overflows. It is
cleared when this register is read.
7 - 0
LBF7
-
LBF0
Loss
of
Basic
Frame
Synchronization Counter. This
eight bit counter will be incremented
once for every 125 microsecond
period in which basic frame
synchronization is lost. It will be
cleared
by
a
basic
frame
6
5
FEBEO E Bit Counter Overflow. This bit is
set to one when the E bit Counter
(page 04H, address 13H & 14H)
overflows. It is cleared when this
register is read.
synchronization to loss of basic
frame
transition.
synchronization
state
Table 57 - Loss of Basic Synchronization Counter
(Page 04H, Address 17H)
JFO
Jitter Attenuator FIFO Counter
Overflow. This bit is set to one
when the Jitter Attenuator FIFO
Counter (page 04H, address 15H)
overflows. It is cleared when this
register is read.
Bit
Name
Functional Description
7 - 0
BR7
-
Bit Error Rate Counter. An eight
bit counter that contains the total
number of errors in the frame
alignment signal.
BR0
4
LBO
Lost
of
Basic
Frame
Synchronization
Counter
Overflow. This bit is set to one
when the Loss of Basic Frame
Synchronization Counter (page 04H
address 17H) overflows. It is
cleared when this register is read.
Table 58 - Bit Error Rate Counter
(Page 04H, Address 18H)
Bit
Name
---
Functional Description
Unused
3
2
BERO Bit Error Rate Counter Overflow.
This bit is set to one when the Bit
Error Rate Counter (page 04H,
address 18H) overflows. It is
cleared when this register is read.
7 - 2
1
RCRC1 RAI and Continuous CRC Error
bit 1. This bit goes high when
received A (RAI) bits were high and
EFO
Errored Frame Alignment Signal
Counter Overflow. This bit is set to
one when the Errored Frame
Alignment Signal Counter (page
04H, address 1AH) overflows. It is
cleared when this register is read.
receive
E
bits
were
low,
continuously, for more than 10
milliseconds, but less than 450
milliseconds. This bit is cleared
when read.
0
RCRC0 RAI and Continuous CRC Error
Bit 0. This bit goes high when
received A (RAI) bits are high and
receive E bits are low, continuously,
for more than 10 milliseconds.
1
0
BPVO Bipolar
Violation
Counter
Overflow. This bit is set high when
the Bipolar Violation Counter (page
04H, address 1CH
&
1DH)
overflows. It is cleared when this
register is read.
Table 59 - RAI With CRC Error Word
(Page 04H, Address 19H)
CCO
CRC Error Counter Overflow. This
bit is set high when the CRC Error
Counter (page 04H, address 1EH &
1FH) overflows. It is cleared when
this register is read.
Table 56 - Overflow Reporting Latch
(Page 04H, Address 16H)
50
MITEL [ MITEL NETWORKS CORPORATION ]
