MT9075B
Preliminary Information
Select Word (page 01H, address 10H, bits 4-0).
Access to the DL is provided by pins TxDLCLK,
TxDL, RxDLCLK and RxDL, which allow easy
interfacing to an external controller.
Frames 1, 3, 5, 7, 9, 11, 13 & 15 of a CRC-4
Addre
ssable
Bytes
Multiframe
F1 F3 F5 F7 F9 F11 F13 F15
NBB0 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4
NBB1 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5
NBB2 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6
NBB3 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7
NBB4 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8
Table 8 - MT9075B National Bit Buffers
Data to be transmit onto the line in the S bit position
a
is clocked in from the TxDL pad (pin 65 in PLCC, pin
62 in MQFP) with the clock TxDLCLK (pin 64 in
PLCC, pin 61 in MQFP). Although the aggregate
clock rate equals the bit rate, it has a nominal pulse
width of 244 ns, and it clocks in the TxDL as if it were
a 2.048 Mb/s data stream. The clock can only be
active during bit times 4 to 0 of the STBUS frame.
The TxDL input signal is clocked into the MT9075B
by the rising edge of TxDLCLK. If bits are selected to
be a part of the DL, all other programmed functions
Note that the Data Link (DL) pin functions, if
selected, override the transmit national bit buffer
function.
for those S bit positions are overridden.
a
The RxDLCLK signal (pin 39 in PLCC, pin 20 in
MQFP) is derived from the receive extracted clock
and is aligned with the receive data link output RxDL.
The HDB3 decoded receive data, at 2.048 Mbit/s, is
clocked out of the device on pin RxDL (pin 40 in
PLCC, pin 21 in MQFP). In order to facilitate the
attachment of this data stream to a Data Link
controller, the clock signal RxDLCLK consists of
positive pulses, of nominal width of 244 ns, during
The CRC-4 Alignment status CALN (page 03H,
address 12H) and maskable interrupt CALNI (page
01H, address 1DH) indicate the beginning of every
received CRC-4 multiframe.
Maskable interrupts are available for change of state
of S bits or change of state of S nibbles. By
a5
a6
writing the proper control bits, an interrupt can be
generated on a change of state of any S bit (except
a
the S bit cell times that are selected for the data
a
S
- normally reserved for the data link), or any
a4
link. Again, this selection is made by programming
address 10H of master control page 01H. No DL
data will be lost or repeated when a receive frame
slip occurs. See Figures 13-16 for timing
requirements.
nibbles for S through S . See the description of
a5
a8
page 01H, address 19H for more details.
In addition, the transparent transmission of channel
0 is supported to meet the ETS requirement.
Selectable on a bit by bit basis, S bits in channel 0
DSTi data can be programmed using register 17H of
page 01H to be sent transparently onto the line.
a
Timeslot 16
Channel 16 may be used to create a transparent 64
kb/s clear channel. In this event CSTi (pin 6 in PLCC,
pin 71 in MQFP) becomes the data input pin for
channel 16 transmit data, and CSTo (pin 5 in PLCC,
pin 70 in MQFP) becomes a 64 kb/s serial output
link. The CSTo output link is synchronous to the
extracted clock timebase. The pin Rx64KCK (pin 47
in PLCC, pin 35 in MQFP) provides a 64 kHz clock
for use with 64 kb/s data emanating from CSTo. The
64 kb/s input data from CSTi is clocked in with an
internal 64 kHz clock synchronous to the I/O pin C4b
(pin 45 in PLCC, pin 33 in MQFP) timebase. The
internal clock toggles coincident with every second
ST-BUS channel boundary, with the first rising edge
of a frame occurring at the beginning of ST-BUS
channel 2.
Data Link Operation
Timeslot 0
The MT9075B has a user defined 4, 8, 12, 16 or 20
kbit/s data link for transport of maintenance and
performance monitoring information across the PCM
30 link. This channel functions using the S bits
a
(S ~S ) of the PCM 30 timeslot zero non-frame
a4
a8
alignment signal (NFAS). Since the NFAS is
transmitted every other frame - a periodicity of 250
microseconds - the aggregate bit rate is a multiple of
4 kb/s. As there are five S bits independently
a
available for this data link, the bit rate will be 4, 8, 12,
16 or 20 kb/s, depending on the bits selected for the
Data Link (DL).
Dual HDLC
The S bits used for the DL are selected by setting
The MT9075B has two identical HDLC controllers
a
the appropriate bits, S ~S , to one in the Data Link
(HDLC0, HDLC1) for the S bits and channel 16
a4
a8
a
16
MITEL [ MITEL NETWORKS CORPORATION ]
