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MT9075BP 参数 Datasheet PDF下载

MT9075BP图片预览
型号: MT9075BP
PDF下载: 下载PDF文件 查看货源
内容描述: E1单芯片收发器 [E1 Single Chip Transceiver]
分类和应用: PC
文件页数/大小: 82 页 / 275 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9075B  
Preliminary Information  
one. Bits 5, 7 and 8 (usually designated X) are spare  
bits and are normally set to one if not used.  
process. First, writing to the internal Command/  
Address Register (CAR) selects one of the 18 pages  
of control and status registers (CAR address: AC4 =  
0, AC3-AC0 = don't care, CAR data D7 - D0 = page  
number). Second, each page has a maximum of 16  
registers that are addressed on a read or write to a  
non-CAR address (non-CAR: address AC4 = 1, AC3-  
AC0 = register address, D7-D0 = data). Once a page  
of memory is selected, it is only necessary to write to  
the CAR when a different page is to be accessed.  
See Figures 11 and 12 for timing requirements.  
Time slot 16 of the remaining 15 basic frames of the  
CAS multiframe (i.e., basic frames 1 to 15) are  
reserved for the ABCD signalling bits for the 30  
payload channels. The most significant nibbles are  
reserved for channels 1 to 15 and the least  
significant nibbles are reserved for channels 16 to  
30. That is, time slot 16 of basic frame 1 has ABCD  
for channel 1 and 16, time slot 16 of basic frame 2  
has ABCD for channel 2 and 17, through to time slot  
16 of basic frame 15 has ABCD for channel 15 and  
30.  
Please note that for microprocessors with read/write  
cycles less than 200 ns, a wait state or a dummy  
operation (for  
C
programming) between two  
successive read/write operations to the HDLC FIFO  
is required.  
MT9075B Access and Control  
Register Access  
Table 5 associates the MT9075B control and status  
pages with access and page descriptions.  
The control and status of the MT9075B is achieved  
through a non-multiplexed parallel microprocessor  
port. The parallel port may be configured for  
Motorola style control signals (by setting pin INT/  
MOT low) or Intel style control signals (by setting pin  
INT/MOT high).  
ST-BUS Streams  
The ST-BUS stream can also be used to access  
channel associated signalling nibbles. CSTo contains  
the received channel associated signalling bits (e.g.,  
ITU-T R1 and R2 signalling), and when control bit  
RPSIG (page 01H, address 1AH) is set to 0, CSTi is  
The controlling microprocessor gains access to  
specific registers of the MT9075B through a two step  
Page Address  
Processor  
Access  
ST-BUS  
Access  
Register Description  
D7 - D0  
00000001 (01H)  
00000010 (02H)  
00000011 (03H)  
00000100 (04H)  
00000101 (05H)  
00000110 (06H)  
00000111 (07H)  
00001000 (08H)  
00001001 (09H)  
00001010 (0AH)  
00001011 (0BH)  
00001100 (0CH)  
00001101 (0DH)  
00001110 (0EH)  
00001111 (0FH)  
00010000 (10H)  
00010001 (11H)  
00010010 (12H)  
Master  
Control  
R/W  
R/W  
R
--  
Master  
Status  
---  
R/W  
R/W  
R
Per Channel Transmit Signalling  
Per Channel Receive Signalling  
CSTi  
CSTo  
Per Time Slot  
Control  
R/W  
R/W  
R
---  
1 Second Status  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
unused  
HDLC0 Control and Status (TS 0)  
HDLC1 Control and Status (TS 16)  
Transmit National Bit Buffer  
Receive National Bit Buffer  
Tx message mode Buffer 0  
Tx message mode Buffer 1  
Rx message mode Buffer 0  
Rx message mode Buffer 1  
R/W  
R/W  
R/W  
R
R/W  
R/W  
R/W  
R/W  
Table 5 - Register Summary  
14