MT90733
CMOS
Advance Information
(such as the FEAC channel), or provided from the
external C-bit interface.
DS3 loopback is controlled by setting a bit in the
memory map. The entire device is used when
loopback is in affect, but the line side input data and
clock are blocked (by the gate preceding the DS3
Framer Block shown in Figure 1).
The capability to generate and transmit single
overhead bit errors is also provided. External
interfaces are provided for transmitting a far end
block error (FORCFEBE), a P-bit parity error
(FORCEPP), a C-bit parity error (FORCECP) and an
overhead bit error (FORCEOE). The FORCEOE
signal is used in conjunction with the enable signal
(OENA) for introducing an overhead bit error in the
next 85-bit segment of the DS3 frame.
The Transmit Frame Reference Generator Block
provides reference timing for bit-serial operation.
This block accepts an external 44.736 MHz clock
signal (TCIN) and derives a clock signal (TCOUT), a
framing pulse (TFOUT), a clock gap signal (TCG)
and a data signal (TDOUT). The TDOUT signal
consists of framing bits and zeros elsewhere.
The microprocessor bus interface consists of eight
bidirectional data and address leads (AD7-AD0),
along with other microprocessor control leads. The
microprocessor bus is used to write control
information and to read status information and
alarms.
Functional Description
The MT90733 (DS3F) is designed for DS3 framer
applications in which broadband payloads are
mapped into the DS3 frame format. Although the C-
bit parity format is recommended, the DS3F can also
operate in the M13 mode. In the C-bit parity format,
the DS3F provides a separate interface for selected
C-bits. The DS3F can transmit and receive the
FEAC channel, generate and detect DS3 AIS, DS3
idle, P-bit parity and C-bit parity.
In addition,
performance counters are provided, as well as the
ability to generate single framing, FEBE, C-bit parity
and P-bit parity errors. The payload interface is
selectable through software as either a bit serial or
nibble-parallel format. Figure 1 shows the block
diagram for the MT90737 (DS3F).
The DS3F receives a DS3 data signal (D3RD) and a
clock signal (D3RC) from a line interface device. The
DS3 receive block performs DS3 frame alignment,
monitors the signal and the input clock for loss of
signal (LOS), out of frame (OOF), and loss of clock
(LOC). A framing error (FE) output is provided to
indicate when any of the 28 framing bits in the DS3
signal are in error.
The DS3 Interpreter Block performs P-bit and C-bit
parity detection and error counting, receive AIS and
idle pattern detection, far end block error (FEBE)
detection and error counting, far end alarm and
control (FEAC) code word detection, C-bit reception,
and X-bit reception. Serial interfaces are provided for
the received X-bits and for 14 of the 21 C-bits. The
clock signal (CRCK) is gapped and is available only
for clocking out C-bits C2, C3 through C6, and C13
through C21. The data communication link clock
(CRDCC) is present only for C-bits C13, C14, and
C15, which are assigned as a data communication
channel. An interface that indicates the state of the
stuff opportunity bit (STUFD) during each of the
seven DS3 subframes and a clock signal (STUFC) is
also provided.
The Output Block provides a bit-serial or a nibble-
parallel interface. The interface is selected by writing
a control bit in the memory map, and is common to
the DS3F receive and transmit circuitry.
In the transmit direction, the Input Block provides
either a serial or parallel interface. The DS3 Send
Block performs P-bit and C-bit parity generation, AIS
and idle pattern generation, far end alarm and
control (FEAC) transmission, X-bit insertion, and C-
bit insertion. The C-bits may be generated internally
(such as C-bit parity), written by the microprocessor
Typical Applications
Figure 3 shows an application of the MT90733 in
wideband data transmission at 44.736Mb/s. The Line
Interface Unit (LIU) interfaces to the line on one side
and to the MT90733 on the other. The MT90733,
with the nibble-parallel interface on the terminal side,
can provide the payload data without the overhead
information. Similarly, the overhead data can be
loaded from the terminal side and mapped into DS3
format by the MT90733. The C-bits may be inserted
internally, written by the microprocessor, or
generated by the external C-bit interface.
Figure 4 shows a video application where the
MT90733 is used for the reception of TV signals and
commands transmission. Simple compression
techniques allow the TV signal to be transmitted and
received in DS3 bandwidth. The bandwidth required
for the command channel in the other direction is
very low.
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MITEL [ MITEL NETWORKS CORPORATION ]
