MT90220
7.4 RX Registers Description
Tables 41 to 55 describe the Receive registers.
Address (Hex):
Direct access
Reset Value (Hex):
100 -107
1 register per link
0C
Bit #
Type
Description
7
R/W
A Value of 0 select to count the number of Stuff cells received by the physical link. A value
of 1 selects to count the total number of cells received by the link.
6
R/W
A value of 1 enables the IMA mode for this link. A value of 0 enables the UNI mode for the
link.
5
4
R/W
R/W
A value of 1 enables the descrambling of the cell for the link
A value of 1 means that the Unassigned cells are discarded upon reception. UNI mode
only.
3
2
R/W
R/W
A value of 1 means that the Idle cells are discarded upon reception. UNI mode only.
A value of 1 enables the discard option of the cells with wrong HEC. A value of 0 will
disables the discard option, all the cells will be written to the receive buffer.
1
0
R/W
R/W
A value of 1signifies that the ATM Forum polynomial value (coset) is not to be added to
the HEC before the verification. A value of 0 means that the HEC as per I.432 only is
calculated and compared (i.e. including the coset).
A value of 1 enables the correction of the cells with a wrong HEC. A value of 0 disable the
correction of the HEC.
Table 41 - RX Link Control Registers
Address (Hex):
Direct access
Reset Value (Hex):
109
1 register for all 8 cell delineation state machines
67
Bit #
Type
Description
7:4
R/W
DELTA parameter value for the Cell Delineation register. The number of consecutive cells
with correct HEC to leave the PRESYNC state to go to the SYNC state. The default value
is 6.
3:0
R/W
ALPHA parameter value for the Cell Delineation register. The number of consecutive cells
with incorrect HEC to leave the SYNC state to go to the HUNT state. The default value is
7.
Table 42 - Cell Delineation Register
Address (Hex):
Direct access
Reset Value (Hex):
108
1 reg. for all 8 cell delineation state machines
0C
Bit #
Type
Description
7:0
R/W
Contains the number of consecutive cell periods that the CD circuit will count before the
incoming ATM cell stream to be considered in LCD state. Each count will be done on a
cell by cell basis. The value of this register is multiplied by 2 before being loaded in the
internal counter. (The internal counter value can be from 0 to 512).
Note that a value of 0 is not allowed as an LCD condition would be generated.
Table 43 - Loss of Delineation Register
52
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