ISO-CMOS MT8940
AC Electrical Characteristics†-Voltages are with respect to ground (V ) unless otherwise stated.(Ref. Figures 11&12)
SS
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
1
C4b output delay (HIGH to
LOW) from C8Kb input/output
Test load circuit 2 (Fig. 17)
on C8Kb.
t
-25
75
ns
84H
2
3
4
5
6
7
C4b output clock period
t
240
123
110
282
165
123
10
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 17).
P4o
C4b output clock width (HIGH)
C4b output clock width (LOW)
C4b output clock rise time
C4b clock output fall time
t
W4oH
t
W4oL
t
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
rC4
t
10
fC4
Frame pulse output delay
(HIGH to LOW) from C4b
t
50
40
ns
ns
FPL
8
Frame pulse output delay
(LOW to HIGH) from C4b
Test load circuit 1 (Fig. 17).
t
FPH
D
P
L
L
9
Frame pulse (F0b) width
C4o delay - LOW to HIGH
C4o delay - HIGH to LOW
t
200
-10
245
45
ns
ns
ns
WFP
4oLH
4oHL
10
11
12
t
t
45
#2
C4b to C2o delay (LOW to
HIGH)
t
t
+10
20
ns
ns
42LH
42HL
13
C4b to C2o delay (HIGH to
LOW)
14
15
16
17
18
19
20
C2o clock period
t
486
244
233
523
291
244
10
ns
ns
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 10).
P2o
C2o clock width (HIGH)
C2o clock width (LOW)
C2o clock rise time
t
W2oH
t
W2oL
t
Test load circuit 1 (Fig. 10).
Test load circuit 1 (Fig. 10).
rC2
C2o clock fall time
t
10
fC2
C2o delay - LOW to HIGH
t
20
2oLH
C2o delay - HIGH to LOW
t
-5
30
2oHL
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C8Kb
as
Output
V
OH
V
OL
C8Kb
as
V
IH
Input
V
IL
t
84H
t
W4oH
V
OH
C4b
F0b
V
OL
t
P4o
t
W4oL
t
t
FPH
FPL
V
OH
V
OL
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
3-39
MITEL [ MITEL NETWORKS CORPORATION ]
