MT8940
ISO-CMOS
Crystal Clock
(12.355 MHz
±
100 ppm)
MT8940
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
Ai
Bi
V
SS
F0b
Y
o
RST
RxA
RxB
RxD
CV
C1.5i
C2i
C4b
F0i
DSTi
DSTo
CSTi
CSTo
C2o
TxT
TxR
RxT
RxR
RECEIVE
TRANSMIT
V
DD
MH89760
MT8980/81
ST-BUS
SWITCH
T1
LINK
(1.544 Mbps)
Crystal Clock
(16.388 MHz
±
32 ppm)
Mode of Operation for the MT8940
DPLL #1 - NORMAL (MS1=0)
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 5 - Synchronization at the Slave End of the T1 Transmission Link
MT8980/81
MT8940
MS0
MS1
MS2
MS3
F0i
C12i
4.096 MHz
System Clock
(ST-BUS
Compatible)
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
Ai
Bi
V
SS
RST
F0b
RxA
RxB
Y
o
RxD
C4b
C2i
C2o
F0i
DSTi
DSTo
CSTi0
CSTi1
CSTo
OUTA
OUTB
RxT
RECEIVE
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - OVERRIDE MAJOR MODES (MS0=X; MS1=X
MS2=1; MS3=0)
TRANSMIT
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
V
DD
MH89790
ST-BUS
SWITCH
Figure 6 - Synchronization at the Master End of the CEPT Digital Transmission Link
Generation of ST-BUS Timing Signals
The MT8940 can source the properly formatted ST-
BUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.
Figure 8 shows two such applications using only
DPLL #2. In one case, the MT8940 is in FREE-RUN
3-34
mode with an oscillator input of 16.388 MHz. This
forces the DPLL to correct at a rate of 4 kHz to
maintain the ST-BUS clocks, which therefore, will be
jittered. In the other case, the oscillator input is
16.384 MHz (exactly eight times the output
frequency) and DPLL #2 operates in NORMAL mode
with C8Kb input tied HIGH. Since no corrections are
necessary, the output is free from jitter. DPLL #1 is
completely free in both cases and available for any
other purpose.
MITEL [ MITEL NETWORKS CORPORATION ]
