ISO-CMOS
MT8940
AC Electrical Characteristics
†
-
Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Ref. Figure 9)
Characteristics
1
2
3
4
5
6
7
8
D
P
L
L
#1
Frame pulse input (F0i) to CVb
output (1.544 MHz) delay
CVb output (1.544 MHz) rise
time
CVb output (1.544 MHz) fall
time
CVb output (1.544 MHz) clock
period
CVb output (1.544 MHz) clock
width (HIGH)
CVb output (1.544 MHz) clock
width (LOW)
CV delay (HIGH to LOW)
CV delay (LOW to HIGH)
Sym
t
F15H
t
r1.5
t
f1.5
t
P15
t
W15H
t
W15L
t
15HL
t
15LH
648
320
314
5
-12
Min
-40
10
12
Typ
‡
Max
75
15
15
690
386
327
30
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test Conditions
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
V
IH
V
IL
t
F15H
t
P15
t
f1.5
t
W15H
CVb
V
OH
V
OL
t
W15L
t
15HL
t
15LH
CV
V
OH
V
OL
t
r1.5
F0i
Figure 9 - Timing Information for DPLL #1 in NORMAL Mode
AC Electrical Characteristics
†
-
Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Ref. Figure 10)
Characteristics
1
2
3
4
5
C8Kb output (8kHz) delay
(HIGH to HIGH)
D
P
L
L
#1
C8Kb output (8 kHz) delay
(LOW to LOW)
C8Kb output duty cycle
Inverted clock output delay
(HIGH to LOW)
Inverted clock output delay
(LOW to HIGH)
Sym
t
C8HH
t
C8LL
50
66
50
t
ICHL
t
ICLH
40
35
75
60
Min
Typ
‡
Max
130
130
Units
ns
ns
%
%
ns
ns
Test Conditions
Test load circuit 2 (Fig. 17).
Test load circuit 2 (Fig. 17).
In Divide -1 Mode
In Divide - 2 Mode
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
3-37
MITEL [ MITEL NETWORKS CORPORATION ]
