MT8924
Preliminary Information
AC Electrical Characteristics - Clocked Timing*
(T
OP
=0 to 70°C; V
DD
=5V5%)
Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Clock period
Clock low level width
Clock high level width
Clock rise time
Clock fall time
Sync. low setup time
Sync. low level hold time
Sync. high setup time
Sync. high width
OS propagation delay from rising
edge of Clock
Cko propagation delay to Clock
edges
TD setup time
TD hold time
TD setup time
TD hold time
Sym
t
CK
t
WLCK
t
WHCK
t
RCK
t
FCK
t
SLSY
t
HLSY
t
SHSY
t
WHSY
t
PDOS
t
PDEC
t
STD
t
HTD
t
STF
t
HTD
80
40
80
40
50
40
80
t
CK
100
80
Min
230
100
100
25
25
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
=50pF
C
L
=50pF
**
Test Conditions
* All AC characteristics are valid 250µs after V
DD
and the clock have been applied. C
L
is the max. capacitive load and R
L
is the test pull up
resistor. With Extra Bit Insert operating mode these times are 80ns longer.
** With Extra Bit Insert operating mode this time becomes 3t
CK
.
t
CK
Cki
t
WHCK
t
WLCK
t
SLSY
F0i
t
HLSY
t
RCK
t
FCK
t
SHSY
t
WHSY
t
STD
TD
t
STF
TF
t
PDEC
t
PDEC
t
HTF
t
HTD
Cko
t
PDOS
OS
Figure 5 - Clock Timing
8-12
MITEL [ MITEL NETWORKS CORPORATION ]
