MT8880C/MT8880C-1 ISO2-CMOS
+5V
3.3k
MT8880C/C-1
6802
IRQ
RS0
IRQ
Address
CS
Peripheral decode
VMA
R/W
Φ2
R/W
E
Data
Data
Figure 15 - MT8880C/C-1 to 6802 Interface
EXAMPLE 1: A software reset must be included at the beginning of all programs to initialize the control
registers after power up. The initialization procedure should be implemented 100ms after power up.
Description
Control
Data
b2
CS
RS0 R/W
b3
b1
b0
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
X
0
0
1
0
X
X
0
0
0
0
X
X
0
0
0
0
X
X
0
0
0
0
X
EXAMPLE 2: Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones
Description
CS
RS0 R/W
b3
b2
b1
b0
1) Write to Control Register A
0
1
1
0
0
0
0
1
1
0
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
3) Write to Transmit Data Register
(send a digit 7)
0
0
0
0
1
0
1
0
1
0
--------------------------------------wait for an interrupt or poll Status Register ----------------------------------------------
4) Read the Status Register
0
1
1
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
(send a digit 5)
0
0
0
0
1
0
1
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
0
1
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
0
0
0
0
1
0
X
0
X
1
X
0
X
1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms).
Figure 16 - Application Hints
4-44
MITEL [ MITEL NETWORKS CORPORATION ]
