MT8880C/MT8880C-1 ISO2-CMOS
BIT
NAME
FUNCTION
DESCRIPTION
b0
BURST
BURST MODE
A logic ‘0’ enables the burst mode. When this mode is
selected, data corresponding to the desired DTMF tone pair
can be written to the Transmit Register resulting in a tone
burst of a specific duration (see AC Characteristics).
Subsequently, a pause of the same duration is induced.
Immediately following the pause, the Status Register is
updated indicating that the Transmit Register is ready for
further instructions and an interrupt will be generated if the
interrupt mode has been enabled. Additionally, if call
progress (CP) mode has been enabled, the burst and pause
duration is increased by a factor of two. When the burst
mode is not selected (logic ‘1’) tone bursts of any desired
duration may be generated.
b1
b2
b3
TEST
S/D
TEST MODE
By enabling the test mode (logic’1’), the IRQ/CP pin will
present the delayed steering (inverted) signal from the DTMF
receiver. Refer to Figure 9 (b3 waveform) for details
concerning the output waveform. DTMF mode must be
selected (CRA b1=0) before test mode can be implemented.
SINGLE /DUAL TONE
GENERATION
A logic ‘0’ will allow Dual Tone Multi-Frequency signals to be
produced. If single tone generation is enabled (logic ‘1’),
either row or column tones (low group or high group) can be
generated depending on the state of b3 in Control Register
B.
C/R
COLUMN/ROW TONES
When used in conjunction with b2 (above) the transmitter
can be made to generate single row or single column
frequencies. A logic ‘0’ will select row frequencies and a logic
‘1’ will select column frequencies.
Table 6. Control Register B Description
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one (b1) Interrupt is inactive. Cleared after
or bit two (b2) is set.
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA
REGISTER FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of the Cleared upon the detection of a
absence of a DTMF signal. valid DTMF signal.
Table 7. Status Register Description
4-42
MITEL [ MITEL NETWORKS CORPORATION ]
