MT8880C/MT8880C-1 ISO2-CMOS
Maximum Series Resistance:150 ohms
Maximum Drive Level: 2mW
V22f + V23f + V24f + .... V2
nf
e.g. CTS Knights MP036S
THD(%) = 100
Toyocom TQC-203-A-9S
Vfundamental
A
number of MT8880C/C-1 devices can be
Equation 1. THD (%) For a Single Tone
connected as shown in Figure 12 such that only one
crystal is required. Alternatively, the OSC1 inputs on
all devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.
V22L + V23L + .... V2nL + V2
+
2H
V23H + .. V2nH + V2
IMD
MT8880C/C-1
MT8880C/C-1
MT8880C/C-1
THD (%) = 100
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
V2L + V2
H
Equation 2. THD (%) For a Dual Tone
OUTPUT FREQUENCY
3.579545 MHz
(Hz)
ACTIVE
INPUT
%ERROR
Figure 12 - Common Crystal Connection
SPECIFIED
697
ACTUAL
699.1
L1
L2
L3
L4
H1
H2
H3
H4
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
Microprocessor Interface
770
766.2
The MT8880C/C-1 employs
a
microprocessor
852
847.4
interface which allows precise control of transmitter
and receiver functions. There are five internal
registers associated with the microprocessor
interface which can be subdivided into three
categories, i.e., data transfer, transceiver control and
transceiver status. There are two registers
associated with data transfer operations.
941
948.0
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
Table 1. Actual Frequencies Versus Standard
Requirements
The Receive Data Register contains the output code
of the last valid DTMF tone pair to be decoded and is
a read only register. The data entered in the Transmit
Data Register will determine which tone pair is to be
generated (see Figure 7 for coding details). Data can
only be written to the transmit register. Transceiver
control is accomplished with two Control Registers
(CRA and CRB) which occupy the same address
space. A write operation to CRB can be executed by
setting the appropriate bit in CRA. The following
write operation to the same address will then be
directed to CRB and subsequent write cycles will
then be directed back to CRA. A software reset must
be included at the beginning of all programs to
initialize the control and status registers after power
up or power reset (see Figure 16). Refer to Tables 3,
4, 5 and 6 for details concerning the Control
Registers. The IRQ/CP pin can be programmed such
that it will provide an interrupt request signal upon
validation of DTMF signals or when the transmitter is
ready for more data (Burst mode only). The IRQ/CP
pin is configured as an open drain output device and
as such requires a pull-up resistor (see Figure 13).
using Equation 2. V and V correspond to the low
L
H
group amplitude and high group amplitude,
2
respectively, and V
is the sum of all the
IMD
intermodulation components. The internal switched-
capacitor filter following the D/A converter keeps
distortion products down to a very low level as
shown in Figure 10.
DTMF Clock Circuit
The internal clock circuit is completed with the
addition of a standard television colour burst crystal.
The crystal specification is as follows:
Frequency:
3.579545 MHz
±0.1%
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Parallel
18pF
4-40
MITEL [ MITEL NETWORKS CORPORATION ]
