MT8880C/MT8880C-1 ISO2-CMOS
Steering Circuit
Guard Time Adjustment
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:
ESt. A logic high on ESt causes v (see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
c
t
= t +t
DP GTP
REC
t =t +t
ID DA GTA
the validation period (t
), v reaches the threshold
GTP
c
The value of t
Electrical Characteristics) and t
is a device parameter (see AC
(V ) of the steering logic to register the tone pair,
DP
TSt
is the minimum
latching its corresponding 4-bit code (see Figure 7)
into the Receive Data Register. At this point the GT
output is activated and drives v to V . GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
REC
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times for tone
c
DD
present (t
) and tone absent (t
). This may be
GTP
GTA
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.
selected, the IRQ/CP pin will pull low when
delayed steering flag is active.
the
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt
)
R
P = (R1R2) / (R1 + R2)
VDD
C1
R2
St/GT
R1
ESt
a) decreasing tGTP; (tGTP < tGTA)
VDD
tGTP = (R1C1) In [VDD / (VDD-VTSt
tGTA = (RpC1) In (VDD/VTSt
RP = (R1R2) / (R1 + R2)
)
)
C1
VDD
VDD
Vc
St/GT
ESt
C1
R1
St/GT
tGTA = (R1C1) In (VDD / VTSt
)
R1
R2
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
ESt
MT8880C/C-1
b) decreasing tGTA; (tGTP > tGTA)
Figure 5 - Basic Steering Circuit
Figure 6 - Guard Time Adjustment
4-36
MITEL [ MITEL NETWORKS CORPORATION ]
