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MT8880CS-1 参数 Datasheet PDF下载

MT8880CS-1图片预览
型号: MT8880CS-1
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS集成DTMFTransceiver [ISO2-CMOS Integrated DTMFTransceiver]
分类和应用:
文件页数/大小: 18 页 / 315 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ISO2-CMOS MT8880C/MT8880C-1  
RS0  
R/W  
FUNCTION  
b3  
b2  
b1  
b0  
0
0
Write to Transmit  
Data Register  
RSEL  
IRQ  
CP/DTMF  
TOUT  
Table 3. CRA Bit Positions  
0
1
1
1
0
1
Read from Receive  
Data Register  
Write to Control  
Register  
b3  
b2  
b1  
b0  
Read from Status  
Register  
C/R  
S/D  
TEST  
BURST  
Table 2. Internal Register Functions  
Table 4. CRB Bit Positions  
BIT  
NAME  
FUNCTION  
DESCRIPTION  
b0  
b1  
TOUT  
TONE OUTPUT  
A logic ‘1’ enables the tone output. This function can be  
implemented in either the burst mode or non-burst mode.  
CP/DTMF  
MODE CONTROL  
In DTMF mode (logic ‘0’) the device is capable of generating  
and receiving Dual Tone Multi-Frequency signals. When the  
CP (Call Progress) mode is selected (logic ‘1’) a 6th order  
bandpass filter is enabled to allow call progress tones to be  
detected. Call progress tones which are within the specified  
bandwidth will be presented at the IRQ/CP pin in  
rectangular wave format if the IRQ bit has been enabled  
(b2=1). Also, when the CP mode and BURST mode have both  
been selected, the transmitter will issue DTMF signals with a  
burst and pause of 102 ms (typ) duration. This signal duration  
is twice that obtained from the DTMF transmitter if DTMF  
mode had been selected. Note that DTMF signals cannot be  
decoded when the CP mode of operation has been selected.  
b2  
b3  
IRQ  
INTERRUPT ENABLE  
REGISTER SELECT  
A logic ‘1’ enables the INTERRUPT mode. When this mode is  
active and the DTMF mode has been selected (b1=0) the IRQ/  
CP pin will pull to a logic ‘0’ condition when either 1) a valid  
DTMF signal has been received and has been present for the  
guard time duration or 2) the transmitter is ready for more data  
(BURST mode only).  
RSEL  
A logic ‘1’ selects Control Register B on the next Write cycle to  
the Control Register address. Subsequent Write cycles to the  
Control Register are directed back to Control Register A.  
Table 5. Control Register A Description  
4-41