MH89770
Preliminary Information
In synchronous operation the slave end of the link
must have its C2 and C1.5 clocks phase locked to
the extracted clock. In plesiochronous clocking
applications where the master and slave end are
operating under controlled slip conditions, phase
locking to the extracted clock is generally not
required.
detailed transformer specification is presented in the
applications section of this data sheet.
To complete the interfaces to the transmit line, a
pre-equalizer and line impedance matching network
is required. The pulse output at the transformer
secondary must be pre-equalized to drive different
lengths of cable. Mitel‘s MH89761 T1 Equalizer is
configurable to provide pre-emphasis for 0-150,
150-450 and 450-655 foot lengths of 22 AWG
transmission line. A separate 6dB pad is also
provided on the MH89761 for use in implementing
external looparound. Both circuits have input and
output impedance of 100Ω. Figure 6 shows how the
equalizer is connected in a typical application. (Refer
to the MH89761 data sheet for more details.)
Mitel’s MT8941 Digital Phase Lock Loop (DPLL) can
be used to generate all timing signals required by the
MH89770. The MT8941 has two DPLLs built into the
device. Figure 5 shows how DPLL #1 can be set up
to generate the C1.5 clock phase locked to the F0i
which in turn is derived from the same source as the
C2 clock. Figure 5 also shows how DPLL #2 is set up
to generate the ST-BUS clocks that are phase locked
to the received data rate. If E8Ko from the MH89770
is connected to the C8Kb input on the MT8941,
DPLL #2 in the device will generate the ST-BUS
clocks that are phase locked to the T1 line.
Line Receiver
The bipolar receiver inputs on the device, RxT and
RxR, are intended to be coupled to the line through a
center tapped pulse transformer as shown in Figure
6. The device presents a 400Ω impedance to the
receive transformer to permit matching to 100Ω
twisted pair cable. The signal detect threshold level
of the receiver circuit is set at approximately 1.5V.
There is no equalization of the received signal. The
receiver circuit is designed to accurately decode a
signal attenuated by a maximum of 3 dB from the
digital crossconnect point. The MH89770 is not
designed to directly accept a signal from the last
network repeater. Interface to the public network
generally requires a Channel Service Unit (CSU).
The receiver decodes the bipolar signal into a split
phase unipolar return to zero format. The two
resulting unipolar signals are used for bipolar
violation detection within the device and are also
output at RxA and RxB. The input jitter tolerance of
the MH89770 is shown in Figure 7.
DS1 Line Interface
Line Transmitter
The transmit line interface is made up of two open
collector drivers (OUTA and OUTB) that can be
coupled to the line with a center tapped pulse
transformer (see Figure 6). A step function is applied
to the transformer when either of the transistors is
turned on. By operating in the transient portion of the
inductance response, the secondary of the
transformer produces an almost square pulse. The
capacitor and inductor on the center tap of the
transmit transformer shown in Figure 6 suppress
transients in the 12 volt supply. The series RLC
across the output of the transformer shape the pulse
to meet the AT & T or CCITT pulse templates. A
Write
Pointer
13 CH
60 CH
2 CH
Wander Tolerance
386 Bit
Elastic
Store
15 CH
47 CH
-13 CH
34 CH
28 CH
Figure 7 - Elastic Buffer Functional Diagram (156 UI Wander Tolerance)
4-138
MITEL [ MITEL NETWORKS CORPORATION ]
