Preliminary Information
MH89770
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 ST-BUS channels peak (26 ST-BUS channels
peak-to-peak). This can be translated into a low
frequency jitter (wander) tolerance value, accounting
for the DS1 to ST-BUS rate conversion, as follows:
Elastic Buffer
The MH89770 has a two frame elastic buffer which
absorbs jitter in the received DS1 signal. The buffer
is also used in the rate conversion between the
1.544 Mbit/s DS1 rate and the 2.048 Mbit/s ST-BUS
data rate.
(1.544/2.048) X 26 X 8 = 156 UI pp.
The received data is written into the elastic buffer
with the extracted 1.544 MHz clock. The data is read
out of the buffer on the ST-BUS side with the system
2.048 MHz clock. The maximum delay through the
buffer is 1.875 ST-BUS frames or 60 ST-BUS
channels, see Figure 7. The minimum delay required
to avoid bus contention in the buffer memory is two
ST-BUS channels.
There is no loss of frame sync, multiframe sync or
any errors in the signalling bits when the device
performs a slip. The information on the FDL pins in
ESF or SLC-96 mode will, however, undergo slips at
the same time.
Framing Algorithm
Under normal operating conditions, the system C2i
clock is phase locked to the extracted E1.5o clock
using external circuitry. If the two clocks are not
phase-locked, then the rate at which the data is
being written into the device on the DS1 side may
differ from the rate at which it is being read out on
the ST-BUS side. The buffer circuit will perform a
controlled slip if the throughput delay conditions
described above are violated. For example, if the
data on the DS1 side is being written in at a rate
slower than what it is being read out on the ST-BUS
side, the delay between the received DS1 write
pointer and the ST-BUS read pointer will begin to
decrease over time. When this delay approaches the
minimum two channel threshold, the buffer will
perform a controlled slip which will reset the internal
ST-BUS read pointers so that there is exactly 34
channels delay between the two pointers. This will
result in some ST-BUS channels containing
information output in the previous frame. Repetition
of up to one DS1 frame of information is possible.
A state diagram of the framing algorithm is shown in
Figure 8. The dotted lines show which feature can be
switched in and out depending upon the operating
mode of the device.
In ESF mode, the framer searches for the FPS bits.
Once this pattern is detected and verified, bit 0 in
Master Status Word 1 is cleared.
When the device is operating in the D3/D4 format,
the framer searches for the FT pattern, i.e., a
repeating 1010... pattern in a specific bit position
every alternate frame. It will synchronize to this
pattern
and
declare
valid
terminal
frame
synchronization by clearing bit 0 in Master Status
Word 1. The device will subsequently initiate a
search for the FS pattern to locate the signalling
frames (see Figure 21). When a correct FS pattern
has been located, bit 3 in Master Status Word 1 is
cleared indicating that the device has achieved
multiframe synchronization.
Conversely, if the data on the DS1 side is being
written into the buffer at a rate faster than it is being
read out on the ST-BUS side, the delay between the
DS1 frame and the ST-BUS frame will increase over
time. A controlled slip will be performed when the
throughput delay exceeds 60 ST-BUS channels. This
slip will reset the internal ST-BUS counters so that
there is a 28 channel delay between the DS1 write
pointer and the ST-BUS read pointer, resulting in
loss of up to one frame of received DS1 data.
Note: the device will remain in terminal frame
synchronization even if no FS pattern can be located.
In D3/D4 format, when the CRC/MIMIC bit in Master
Control Word 1 is cleared, the device will not go into
synchronization if more than one bit position in the
frame has a repeating 1010.... pattern, i.e., if more
than one candidate for the terminal framing position
is located. The framer will continue to search until
only one terminal framing pattern candidate is
discovered. It is, therefore, possible that the device
may not synchronize at all in the presence of PCM
code sequences (e.g., sequences generated by
some types of test signals) which contain mimics of
the terminal framing pattern.
Figure 7 illustrates the relationship between the read
and write pointers of the receive elastic buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the writer
pointer a frame slip will occur, which will put the read
pointer 34 channels from the write pointer.
Conversely, if the read pointer moves more than 60
channels from the write pointer, a slip will occur,
4-139
MITEL [ MITEL NETWORKS CORPORATION ]
