Preliminary Information
MH88620BR
-VBat
CSTi
C2i
FDi
-5 +5
+5V
SYSTEM
GROUND
VDD
VR
VX
RX
DSTo
DSTi
VBAT
CODEC
SUBSCRIBER 1
GRX0
GRX1
LCA
VEE
SDo
CA
FLi
-5V
TERM
Timeslot
Assignment
Circuit
TX
AGND
TF1
GTX0
GTX1
SHK
F1i
CA
C2i
TF2
Status
Mux
CSTo
Circuit
Z1
Z2
TIP
P
R
O
T
E
C
T
I
RNGC
VRLY
K1
RRD
RING
RF1
O
N
REVC
RF2
+
~
45Vrms
20Hz
45VRMS 20Hz
~
+
NS
-VBat
Figure 7b - OPS SLIC Configuration Applications Circuit - Balanced Ringing
2-157