ACE9050
Write Cycle (Normal Mode)
t
ECLK
ECLK
ADDR
t
AD
V
WE
H
CS
t
WE
H
AD
I
t
AD
V
CS
L
WEN
t
CS
L
WE
H
t
WE
L
WE
H
DATA
t
WE
H
CS
H
t
AD
V
DA
LZ
t
DA
V
WE
H
t
WE
H
DA
I
Fig. 5 ACE9050 6303 Write cycle timing diagram
Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz.
Worst case timings:
T
AMB
=
240°C
to
185°C,
V
DD
=
13·6V
to
15·5V
Typical timings:
T
AMB
=
125°C,
V
DD
=
13·75V
Normal clock
Description
Cycle time
Address valid to end of Write
Address hold time
Chip enable set-up time
WE pulse width
Data valid set-up time
Data hold time
Address valid to data low Z
Address valid to chip select
WE high to CS high
Symbol
Min.
Typ.
992
853
140
840
364
368
473
5
140
Max.
Min.
Turbo clock
Typ.
496
420
72
415
181
183
225
4
72
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ECLK
t
AD
V
WE
H
t
WE
H
AD
I
t
CS
L
WE
H
t
WE
L
WE
H
t
DA
V
WE
H
t
WE
H
DA
I
t
AD
V
DA
LZ
t
AD
V
CS
L
t
WE
H
CS
H
835
125
825
363
365
120
451
0
127
862
151
860
371
371
487
10
163
395
63
390
173
177
60
203
0
66
427
93
425
184
192
239
9
105
Table 4 ACE9050 6303 Write cycle timing
8
MITEL [ MITEL NETWORKS CORPORATION ]
