ACE9050
EMULATION MODE PROCESSOR INTERFACE
Read and Write Cycles
t
CYC
ECLK
AS
t
EC
L
RW
V
R/W
INVALID
STABLE
INVALID
t
EC
L
AD
V
A[15:8]
t
EC
L
AD
I
t
AD
V
AS
L
A[7:0]/D[7:0]
AD[7:0]
t
AS
L
AD
I
t
DA
V
DA[7:0]
t
DA
I
Fig.6 ACE9050 6303 Emulation mode Read/Write cycles timing diagram
Emulation Mode Timing Cycle Conditions
Input clock ECLK frequency = 1·008MHz (Normal clock), 2·016MHz (Turbo clock), T
AMB
=
125°C,
V
DD
=
15V 610%
Normal clock
Description
Cycle time
Read/Write settling time
Address delay time
Address hold time
Address to latch set-up time
Address to latch hold time
Data set-up time - WRITE
Data hold time - WRITE
Data set-up time - READ
Data hold time - READ
Symbol
Min.
Typ.
992
250
250
0
60
30
50
1
80
1
0
20
20
50
1
80
1
Max.
Min.
Turbo clock
Typ.
496
160
160
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC
t
EC
L
RW
V
t
EC
L
AD
V
t
EC
L
AD
I
t
AD
V
AS
L
t
AS
L
AD
I
t
DA
V
-W
t
DA
I
-W
t
DA
V
-R
t
DA
I
-R
Table 5 6303 Emulation Mode Read/Write cycles timing
9
MITEL [ MITEL NETWORKS CORPORATION ]
