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ACE9030MIWFP2Q 参数 Datasheet PDF下载

ACE9030MIWFP2Q图片预览
型号: ACE9030MIWFP2Q
PDF下载: 下载PDF文件 查看货源
内容描述: 无线接口和双合成器 [Radio Interface and Twin Synthesiser]
分类和应用: 无线
文件页数/大小: 39 页 / 382 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ACE9030  
COMPENSATION  
CHARGE PUMP  
TIME GATING  
SET CURRENT  
Ico  
COMPENSATION  
DAC  
CHARGE TO  
LOOP FILTER  
COMPARISON  
FREQUENCY  
ACCUMULATOR  
MODULO-5 OR 8  
OVERFLOW  
(TO PRESCALER  
MODULUS CONTROL)  
FRACTION  
NF  
REGISTER  
Fig. 25 Fractional-N Add-On To Main Synthesiser  
and so increment the total division.  
when none are needed. Similarly in 1/8’s mode if 1/4 ( and 3/4 )  
or /2 fractions are set then the LSB or two LSB’s in the  
accumulator will be forced to zero to relax the tolerance on the  
compensation.  
1
To avoid loop modulation due to the accumulating phase  
shift at the fractional frequency, a compensation charge must  
also be driven onto the loop filter to track the accumulated  
phase error so a current Icomp(0) is output on PDP for a fixed  
short duration. Icomp(0) is given by Icomp(0) = ACC x Ico,  
where ACC is the value of the phase accumulator and Ico is  
a current set by a resistor on pin RSC such that Ico = IRSC/320.  
InatypicalsystemtherequiredvalueofIcoisbetween1/10 and  
1/3 of Ibo and thus the resistor on RSMA has a value between  
one and three times the value of the resistor on RSC. As with  
RSMA, the pin RSC does not need any decoupling and to  
avoid all possibilities of oscillation the external capacitance  
shouldbelessthan5pF. Forafulldescriptionofthismodesee  
the later section “Detailed Operation of Fractional-N Mode”.  
In fractional-N mode a zero fraction numerator, in both  
1/5’s and 1/8’s mode, will force the accumulator to zero and not  
simply leave it at an arbitrary fixed value. This feature makes  
testing easier by setting the accumulator to a known state, but  
isalsousefulinoperationbystoppingallcompensationpulses  
MainSynthesiser-Fractional-NModewithSpeed-up  
In Fractional-N mode with Speed-up the normal compen-  
sation current is increased by the same factor (2L+1) as the  
main charge pump current to give Icomp(1), and at the same  
time the integrating capacitor is also driven with a compensat-  
ingchargebyacurrentIcomp(2)settoIcomp(1)xK.Thisextra  
compensation is included so that the loop will step to exactly  
thedesiredfrequencyduringtheSpeed-upphaseandthenbe  
on channel when normal Fractional-N begins.  
Main Synthesiser Charge Pumps  
The charge pumps for all modes are shown together in  
figure 26. The charge pumps on pin PDP are used normally to  
hold a channel and are also used in speed-up modes at a  
To VCO  
VDD  
VDD  
Icomp(0) =  
ACC.Ico  
Icomp(1) =  
x2, 4, 8, 16  
φ
Icomp2 =  
K.Icomp(1)  
Fc  
UP  
Icomp(0) =  
CN.lbo  
Iprop(1) =  
x 2, 4, 8, 16  
φ
Fc  
UP  
PDP  
Ri  
lint =  
K.lprop(1)  
φ
DOWN  
Cp  
PDI  
φ
Ci  
DOWN  
VSS (GND)  
INTEGRAL  
CHARGE PUMP  
EXTERNAL,  
PASSIVE  
LOOP FILTER  
Cp, Ri, Ci  
FRACTIONAL-N  
FRACTIONAL-N  
COMPENSATION  
CHARGE PUMP  
(PROPORTIONAL)  
PROPORTIONAL  
CHARGE PUMP  
COMPENSATION  
CHARGE PUMP  
(INTEGRAL)  
Fig. 26 Main Synthesiser Charge Pumps  
27  
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