AS42C4064 883C
64K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
FUNCTIONAL DESCRIPTION
goes LOW, to select between a MASKED-WRITE cycle and
a normal WRITE cycle. If (ME)/ WE is LOW at the RAS
HIGH-to-LOW transition, a MASKED-WRITE operation is
selected. For a normal DRAM WRITE operation, (ME)/
WE must be HIGH at the RAS HIGH-to-LOW transition.
(ME)/ WE is a “don’t care” at the RAS HIGH-to-LOW
transition for a DRAM READ cycle.
If (ME)/ WE is LOW when CAS goes LOW, a DRAM
WRITE operation is performed and the data present on the
DQ1-DQ4 port will be written into the selected memory
cells. If ME/ (WE) is LOW when RAS goes LOW, the input
data will be “masked” before being stored in the DRAM.
The VRAM can perform all the normal DRAM cycles
including EARLY-WRITE, LATE-WRITE, READ-WRITE,
READ-MODIFY-WRITE, PAGE-MODE READ, PAGE-
MODE WRITE and PAGE-MODE READ-MODIFY-
WRITE. Refer to the AC timing parameters and diagrams
in this data sheet for more details on these operations.
The VRAM can be divided into three functional blocks;
the DRAM, the transfer control circuitry, and the serial
access memory (SAM). All of the operations described
below are also shown in the AC Timing Diagrams of this
section and are summarized in the Truth Table.
Note:
For dual function pins, the function that is not being
discussed will be surrounded by parenthesis. For
example, the TR/OE pin will be shown as TR/(OE) in
references to transfer operations.
DRAM OPERATION
The DRAM portion ofthe VRAM is functionally identical
to standard 64K x 4 DRAMs. However, because several of
the DRAM control pins are used for additional functions on
this part, several conditions that were undefined or “don’t
care” states for the DRAM are specified for the VRAM.
These conditions are highlighted in the following discus-
sion.
MASKED-WRITE
If ME/ (WE) is LOW at the RAS HIGH-to-LOW transi-
tion, the data (mask data) present on the DQ1-DQ4 inputs
will be written into the bit mask data register. The mask
data acts as an individual write enable for each of the four
DQ-DQ4 pins. If a LOW (logic 0) is written to a mask data
register bit, the input port for that bit is disabled during the
subsequent WRITE operation and no new data will be
written to that DRAM cell location. A HIGH (logic 1) on a
mask data register bit enables the input port and allows
normal WRITE operations to proceed. Note that CAS is still
HIGH. When CAS goes LOW, the bits present on the DQ1-
DQ4 inputs will be written to the DRAM (if the mask data
bit was HIGH) or ignored (if the mask data bit was LOW).
The DRAM contents that correspond to the masked bits will
not be changed during the WRITE cycle. Since the mask
data register is reset (to all 1s) at the end of every MASKED-
WRITE cycle, new mask data must be supplied at the
beginning of each MASKED-WRITE cycle. An example of a
typical MASKED-WRITE cycle is shown in Figure 1.
READ/WRITE Cycles
The 16 address bits that are used to select a 4-bit word
from the 65,536 x 4 available are latched into the chip using
the A0-A7, RAS, and CAS inputs. First, the 8 row-address
bits are set up on the address inputs and clocked into the
part when RAS transitions from HIGH-to-LOW. Next, the
8 column address bits are set up on the address inputs and
clocked-in when CAS goes from HIGH-to-LOW.
For single port DRAMs, the OEpin is a “don’t care” when
RAS goes LOW. For the VRAM, (TR)/ OE is used, when
RAS goes LOW, to select between an internal transfer
operation and a DRAM operation. (TR)/ OE must be HIGH
at the RAS HIGH-to-LOW transition for a DRAM port
READ or WRITE operation.
If (ME)/ WE is HIGH when CAS goes LOW, a DRAM
READ operation isperformed and thedata from thememory
cells selected will appear at the DQ1-DQ4 port. The (TR)/
OE input must be LOW to enable the DRAM output port.
For single port DRAMS, WE is a “don’t care” when RAS
goes LOW. For the VRAM, (ME)/ WE is used, when RAS
AS42C4064 883C
REV. 3/97
DS000013
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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3-4
MICROSS [ MICROSS COMPONENTS ]
