AUSTIN SEMICONDUCTOR, INC.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
VRAM
AVAILABLE AS MILITARY
SPECIFICATION
• MIL-STD-883
64K x 4 DRAM
WITH 256 x 4 SAM
PIN ASSIGNMENT (Top View)
24-Pin DIP
(D-11)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Industry standard pinout, timing and functions
High-performance, CMOS silicon-gate process
Single +5V
±10%
power supply
Inputs and outputs are fully TTL and CMOS
compatible
Refresh modes:
/
R
/
A
/
S-ONLY,
/
C
/
A
/
S-BEFORE-/R
/
A
/
S, and
HIDDEN
256-cycle refresh within 4ms
Optional PAGE MODE access cycles
Dual port organization: 64K x 4 DRAM port
256 x 4 SAM port
BIT MASK WRITE mode capability on DRAM port
No refresh required for serial access memory
Fast access times: 100ns parallel, 30ns serial
Specifications guaranteed over full military tempera-
ture range (-55°C to +125°C)
SC
SDQ1
SDQ2
1
2
3
24
23
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
CAS
A0
A1
A2
A3
A7
OPTIONS
• Timing (DRAM, SAM)
100ns, 30ns
120ns, 35ns
• Packages
Ceramic DIP (400 mil)
NOTE: Consult factory for other package options.
22
ED
TR/OE
4
D
21
20
DQ1
5
E N NS
M
DQ2
I G
19
M
ME/WE
6
Y
18
7
O
E S
LI
–
T
C
D
RAS
I
8
17
E
AB
MARKING
R E W
VAIL
A6
9
16
T
N
ED A
15
A5
10
O R
IT
N O
IM
14
A4
11
13
Vcc
12
F
–L
-10
-12
C
No. 107
GENERAL DESCRIPTION
The AS42C4064 883C is a high-speed, dual port CMOS
dynamic random access memory, or video RAM (VRAM)
containing 262,144 bits. These bits may be accessed by a 4-
bit-wide DRAM port or by a 256 x 4 bit serial access memory
(SAM) port. Data may be transferred bidirectionally be-
tween the DRAM and the SAM.
The DRAM portion of the VRAM is functionally identical
to the MT4067 (64K x 4) bit DRAM. Four 256-bit data
registers make up the serial access memory portion of the
VRAM. Data I/O and internal data transfer are accom-
plished using three separate bidirectional data paths; the
4-bit random access I/O port, the four internal 256-bit wide
paths between the DRAM and the SAM, and the 4-bit serial
I/O port for the SAM. The rest of the circuitry consists of the
control, timing and address decoding logic.
Each of the ports may be operated asynchronously and
independently of the other except when data is being trans-
ferred internally between them. As with all DRAMs, the
VRAM must be refreshed in order to maintain data. The
refresh cycles must be timed so that all 256 combinations of
/
R
/
A
/
S addresses are executed at least every 4ms (regardless
of sequence). Austin Semiconductor recommends evenly
spaced refresh cycles for maximum data integrity. An inter-
nal transfer between the DRAM and the SAM counts as a
refresh cycle. The SAM portion of the VRAM is fully static
and does not require any refresh.
AS42C4064 883C
REV. 3/97
DS000013
3-1
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
MICROSS [ MICROSS COMPONENTS ]
