AUSTIN SEMICONDUCTOR, INC.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
TRANSFER OPERATION
DRAM-TO-SAM TRANSFER (READ TRANSFER)
A TRANSFER operation is initiated when
/
T
/
R/(/O
/
E) is
LOW at
/
R
/
A
/
S (HIGH-to-LOW) time. (?M
/
E)/?W
/
E indicates the
direction of the transfer and must be HIGH as
/
R
/
A
/
S goes
LOW for a DRAM-TO-SAM TRANSFER. In this case, the
row address bits indicate the four 256-bit DRAM rows that
are to be transferred to the four SAM data registers, and the
column address bits indicate the start address of the next
SERIAL OUTPUT cycle from the SAM data registers.
/
R
/
A
/
S
and
?
C
/
A
/
S are used to strobe the address bits into the part. To
complete the TRANSFER,
/
T
/
R/(/O
/
E) is taken HIGH while
/
R
/
A
/
S and
?
C
/
A
/
S are still LOW. The 1,024 bits of DRAM data
are then written into the SAM data registers and the serial
shift start address is stored in an internal 8-bit register.
There must be no rising edges on the serial clock (SC) input
while the transfer is taking place (refer to the AC timing
diagrams). A REAL-TIME READ TRANSFER cycle is the
only time when SC must be synchronized with the DRAM
/
R
/
A
/
S and
?
C
?
A
/
S timing. If
/
S
/
E is LOW, the first bits of the new
row data will appear at the serial outputs with the next SC
clock pulse.
/
S
/
E enables the serial outputs and may be either
HIGH or LOW during this operation.
SAM-TO-DRAM TRANSFER (WRITE TRANSFER)
The SAM-TO-DRAM TRANSFER operation is identical
to the DRAM-TO-SAM TRANSFER described above ex-
cept that (?M
/
E)/?W
/
E and
/
S
/
E must be LOW when
/
R
/
A
/
S goes
LOW. The row address indicates the DRAM row to which
the SAM data registers will be written, and the column
address indicates the starting address of the next SERIAL
INPUT cycle for the SAM data registers. If
/
S
/
E is HIGH when
/
R
/
A
/
S goes LOW, a SERIAL-INPUT-MODE ENABLE cycle is
performed.
SERIAL-INPUT-MODE ENABLE
(PSEUDO WRITE TRANSFER)
It is possible to change the direction of the SAM port from
output to input without performing a SAM-TO-DRAM
TRANSFER. This operation, called a SERIAL-INPUT-MODE
ENABLE cycle, is simply a SAM-TO-DRAM TRANSFER
cycle with
/
S
/
E held HIGH instead of LOW. The DRAM data
will not be disturbed and the data registers will be ready to
accept input data.
The only way to put the SAM port in the SERIAL OUT-
PUT mode is to do a DRAM-TO-SAM TRANSFER.
SERIAL INPUT and SERIAL OUTPUT
The control inputs for SERIAL INPUT and SERIAL OUT-
PUT are SC and
/
S
/
E. The rising edge of SC increments the
serial address counter and provides access to the next SAM
location.
/
S
/
E enables or disables the serial input/output
buffers.
SERIAL OUTPUT of the SAM data register contents will
start at the serial start address that was loaded during the
DRAM-TO-SAM TRANSFER cycle. The SC input incre-
ments the address counter and presents the contents of the
next SAM location to the 4-bit port.
/
S
/
E is used as an output
enable during the SAM output operation. The serial ad-
dress is automatically incremented with every SC LOW-
TO-HIGH transition, regardless of whether
/
S
/
E is HIGH or
LOW, however, wrap around to location 0 will NOT occur
after reaching its maximum count of 255 but rather incre-
ment to a count of 511 before preforming a wrap around to
location 0.
SC is also used to clock-in data when the device is in
SERIAL INPUT. As in serial output operation, the contents
of the serial address register, which was loaded when the
serial input mode was enabled, will determine the serial
address to which the first bit will be written.
/
S
/
E acts as an
enable for serial data input and must be LOW for normal
serial input. If
/
S
/
E is HIGH, the data inputs are disabled and
the SAM contents will not be modified. The serial address
register is incremented with every L
>
H transition of SC,
regardless of the logic level on the
/
S
/
E input and in the same
manner as previously stated.
SAM OPERATION
SERIAL INPUT/OUTPUT MODE CONTROL
The SAM port is automatically placed in the serial output
mode after a DRAM-TO-SAM TRANSFER operation. Con-
versely, after a SAM-TO-DRAM TRANSFER the SAM port
will be in the serial input mode.
AS42C4064 883C
REV. 3/97
DS000013
3-6
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
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