PEM
AS28F128J3A
Q-Flash
Read Operations
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
Min
115
Max
‐
‐
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1,2
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
R1
R2
R3
R4
R5
R6
R7
R8
R9
Read/Write Cycle Time
Address to Output Delay
CEX to Output Delay
115
1,2
115
‐
1,2
OE# to Non‐Array Output Delay
RP# High to Output Delay
CEX to Output in Low Z
OE# to Output in Low Z
CEX High to Output in High Z
OE# High to Output in High Z
‐
‐
50
210
‐
1,2,4
1,2
0
0
‐
1,2,5
1,2,5
1,2,5
1,2,5
‐
25
15
‐
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First
tOH
R10
0
‐
ns
1,2,5
tELFL/tELFH
R11
R12
R13
R14
R15
R16
CEX Low to BYTE# High or Low
BYTE# to Output Delay
‐
‐
10
1
ns
ns
µs
µs
ns
ns
1,2,5
1,2
tFLQV/tFHQV
tFLQZ
BYTE# to Output in High Z
CEx High to CEx Low
‐
1
1,2,5
1,2,5
5,6
tEHEL
0
‐
‐
tAPA
Page Address Access Time
OE# to Array Output Delay
25
25
tGLQV
‐
1,2,4
Notes
1. CEX low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CEX high is defined as the combination of pins CE0, CE1, and CE2 that disable
the device
2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX
4. See Figure 13, “AC Input/Output Reference Waveform” , “Transient Equivalent Testing Load Circuit” for testing characteristics.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Micross Components reserves the right to change products or specifications without notice.
AS28F128J3A
Rev. 5.8 8/13
6
MICROSS [ MICROSS COMPONENTS ]
