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AS28F128J3APBG-15/XT 参数 Datasheet PDF下载

AS28F128J3APBG-15/XT图片预览
型号: AS28F128J3APBG-15/XT
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 128MX16, PBGA64, PBGA-64]
分类和应用: 内存集成电路
文件页数/大小: 15 页 / 1217 K
品牌: MICROSS [ MICROSS COMPONENTS ]
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PEM  
AS28F128J3A  
Q-Flash  
Single-Word Asynchronous Read Waveform  
R1  
R2  
Address [A]  
R8  
R3  
R4  
CEx [E]  
OE# [G]  
R9  
WE# [W]  
R7  
R10  
R6  
DQ[15:0] [Q]  
R13  
R11  
R12  
BYTE# [F]  
R5  
RP# [P ]  
Notes  
1. CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the combination of pins CE0, CE1, and CE2 that disable  
the device  
2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,query reads, or device identifier reads).  
8-Word Asynchronous Page Mode Read  
R1  
R2  
A[MAX:4] [A]  
000  
R3  
001  
110  
111  
A[3:1] [A]  
CEx [E]  
OE# [G]  
R4  
R8  
WE# [W]  
R7  
R10  
R15  
R10  
R6  
R9  
1
2
7
8
DQ[15:0] [Q]  
RP# [P]  
R5  
BYTE# [F]  
Notes  
1. CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the combination of pins CE0, CE1, and CE2 that disable  
the device  
2. In this diagram, BYTE# is asserted high.  
Micross Components reserves the right to change products or specifications without notice.  
AS28F128J3A  
Rev. 5.8 8/13  
7