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5962-9318706H5C 参数 Datasheet PDF下载

5962-9318706H5C图片预览
型号: 5962-9318706H5C
PDF下载: 下载PDF文件 查看货源
内容描述: [SRAM Module, 128KX32, 45ns, CMOS, PGA-66]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 11 页 / 259 K
品牌: MICROSS [ MICROSS COMPONENTS ]
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SRAM  
AS8S128K32  
Austin Semiconductor, Inc.  
NOTES  
1. All voltages referenced to VSS (GND).  
2. -3v for pulse width <20ns.  
3. ICC is dependent on output loading and cycle rates.  
The specified value applies with the outputs  
7. At any given temperature and voltage condition,  
tHZCE, is less than tLZCE, and tHZWE is less than tLZWE  
8. WE is HIGH for READ cycle.  
.
9. Device is continuously selected. Chip enables and output  
enable are held in their active state.  
10. Address valid prior to or coincident with latest occurring  
chip enable.  
11. tRC= READ cycle time.  
12. Chip enable (CE) and write enable (WE) can initiate and  
terminate a WRITE cycle.  
1
open, and f=  
HZ.  
tRC(MIN)  
4. This parameter is sampled.  
5. Test conditions as specified with output loading as  
shown in Fig. 1 unless otherwise noted.  
6. tHZCE, tHZOE and tHZWE are specified with CL= 5pF  
as in Fig. 2. Transition is measured +/- 200 mV  
typical from steady state coltage, allowing for actual  
tester RC time constant.  
13. 32 bit operation  
DATA RETENTION ELECTRICAL CHARACTERISTICS  
DESCRIPTION  
CONDITIONS  
SYMBOL  
MIN  
MAX  
UNITS  
NOTES  
VCC for Retention Data  
VDR  
2
--  
V
CE\ > VCC - 0.2V  
IN > VCC - 0.2V  
VCC = 2.0V  
VCC = 3V  
ICCDR  
ICCDR  
--  
--  
6
mA  
mA  
Data Retention Current  
V
11.6  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
0
--  
ns  
ns  
4
tRC  
4, 11  
Operation Recovery Time  
LOWVCC DATA RETENTIONWAVEFORM  
DATA RETENTION MODE  
>2V  
VDR  
4.5V  
4.5V  
Vcc  
tCDR  
tR  
VIH  
CE\  
VDR  
V
IL  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS8S128K32  
Rev. 3.5 7/00  
5
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