DATA SHEET
VSP 94x2A
ferent blocks, the data is made valid with the same V-
Sync related signals mentioned above for the write
process.
2
Table 3–5: I C bus clock domains
Domain
CP-CD
CP-PP
Description
CVBS frontend
LL-PLL
Clock
The VSP 94x2A distinguishes between two different
types of read-registers. The behavior of the “normal”
read registers does not differ from the behavior of the
write registers. Only the direction of the data flow is
opposite.
CP
FP
CLKF20
CLKF20
CLKF20
CLKF40
CLKF40
CLKF40
CLKF40
CP-I2C
FP-PRE
FP-MC
FP-RGB
FP-TNR
I2C read
The “rs typ” read registers behave differently. They can
be only set (means value 1) by the internal blocks
using the rising edge of a corresponding signal. After
Prescaler
Memory-controller
RGB Frontend
2
reading by the I C bus master, the registers will be
2
automatically reset (means value 0) by the I C bus ker-
nel/interface. For example the register NMSTATUS
belongs to the “rs typ” read registers. NMSTATUS sig-
nalizes a new value for NOISEME. So if NMSTATUS is
read as ‘0’ the current noise measurement has not
been updated. If the NMSTATUS is read as ‘1’ a new
noise measurement value can be read. All other “rs
typ” read registers work in the same way. The “rs typ”
read registers will be marked in the overview with the
short cut “rstyp” or will have the additional hint “Note:
Temporal noise
reduction
FP-I2C
PP
I2C read
CLKF40
CLKF36
CLKF36
CLKB36
CLKB36
CLKB36
CLKB36
PP
BP
LL-PLL
PP-I2C
BP-DP
I2C read
Display processing
Pixel-Mixer
2
reset automatically when read/write” in the detailed I C
bus command description.
BP-PM
BP-ODC
BP-ODC/MC
Output data control
By default all registers are made valid by the internal V-
Sync related signals and, in addition, a store command
has to be sent for write registers. The registers, which
should also be made available immediately as for writ-
ing and reading, are marked with the short cut NTO
(No take over mechanism).
Output data control/
memory-controller
BP-POS
BP-DAC
BP-I2C
Postscaler
CLKB36
CLKB72
CLKB36
DAC processing
I2C read
Registers which need a hand-shake mechanism
2
between the I C bus interface and the different blocks
are marked with the shortcut HS (Hand shake mecha-
nism). This means that all bits of the registers are used
when the last register is written. After PPLIP9-2 is writ-
ten, PPLIP1-0 must be written to allow these bits to
have effect.
The I2C parameter V20STAT, V40STAT and V36BSTAT
reflect the state of the register values.
The registers for the write parameter STOPMODE are
If these bits are read as ‘1’, then the store command
was sent, but the data is not made available yet.
directly connected to the read registers of the parame-
ter SMMIRROR. So it is possible to check the I C bus
2
protocol by writing and reading to the register STOP-
MODE and SMMIRROR, respectively.
If these bits are ‘0’ then the data was made valid and a
new write or read cycle can start.
The transmitted data is internally stored in registers.
Writing to or reading from a non-existant register is
permitted and does not generate a fault by the IC.
The bits V20STAT, V40STAT and V36BSTAT may be
checked before writing or reading new data, otherwise
data can be lost by overwriting. No V36FSTAT register
exist. To make the register values available to the four
I C bus interface immediately after sending, the I C
bus master has to write a ‘don’t care’ byte to the sub-
address FEh (store command).
After switching on the IC, all bits of the VSP 94x2A are
set to defined states, (refer to Table 3–6). POR is set
after reset to pin 24. It stays ‘1’, until it is cancled via
software PORCNCL. This can be used to decide dur-
ing TV operation, whether to program all registers (e.g.
after power failure reset) or only altered ones (normal
TV operation).
2
2
2
For the read process, the I C bus master must not
send a store command. In order to have a defined time
2
step for the I C bus interface blocks in the different
domains, where the data will be available from the dif-
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Aug. 16, 2004; 6251-552-1DS
35
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