VSP 94x2A
DATA SHEET
2.6.1. Line-locked Clock Generator
A freerunning frequency is also generated which may
be selected alternatively. The freerunning frequency
for the 100/120 Hz version dependent on FRINC is
The clock generation system derives all clocks from
one 20.25 MHz crystal oscillator clock source. An
internal PLL multiplies this oscillator frequency by 32,
generating a clock of 648 MHz which is used as refer-
ence for all clocks needed.
f
= FRINC ⋅ 103Hz
displayfr
Line-locked horizontal sync pulses are generated by a
digital phase locked loop. The time constant can be
adjusted between fast and slow behavior (KPL, KIL) to
accommodate different backend ICs. The PLL control
can be frozen up to 15 lines before V-sync (FION) for a
duration up to 15 lines (FILE). This may be used to
reduce disturbances by h-phase errors which are pro-
duced by VCR’s. The output frequency for the 100/120
Hz version dependent on IICINCR is
Normally, IICINCR and FRINC are equal or nearly the
same. The value is internally divided by two for the 50/
60 Hz versions.
The number of pixels generated by the PLL is given by
PPLIP. For line-locked clock generation the following
equation must be fulfilled:
PPLIP = 2 ⋅ PPLOP
f
= IICINCR ⋅ 103Hz
displayll
20.25 MHz
CLKF40
CLKF20
xtal
oscillator
frequency
divider
FRINC
PLL
648MHz
frequency
divider
FR-DTO
M
U
X
CLKB27
CLKB36
CLKB72
inter-
polation
sync-
separation
phase
detector
loop
filter
frequency
divider
ADC
LL-DTO
IICINCR
analog
CVBS
locked or
freerunning
selection
line-locked
Fig. 2–42: Line-locked Clock Ceneration
nominal 50Hz
operation (analog out)
13.5 / 18
27 / 36 MHz
nominal 50Hz
operation (digital out)
nominal 100Hz
operation (analog out)
nominal 100Hz
operation (digital out)
Fig. 2–43: Allowed Operation Area for Clock Generation
32
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
