DATA SHEET
VSP 94x2A
2
Table 3–6: I C bus characterization, continued
Subaddress
98h
Default
R/W
R
Take-over Subaddress
Default
00h
R/W
W
Take-over
V40
V36B
V20
NTO
NTO
NTO
NTO
NTO
V20
V20
V40
V40
V40
V40
V40
V40
NTO
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
99h
R
00h
W
V40
A0h
00h
00h
FFh
FFh
00h
10h
00h
00h
00h
00h
00h
00h
00h
W
W
W
W
W
W
W
W
W
W
W
W
W
R
00h
W
V40
A1h
00h
W
V40
A2h
00h
W
V40
A3h
00h
W
V40
A4h
00h
W
V40
B0h
00h
W
V40
B1h
00h
W
V40
EAh
EBh
ECh
EDh
EEh
EFh
F0-F6h
F7h-FDh
FEh
(spare)
W
W
FFh
Take-over mechanism
Register types
NTO
V20
No take-over mechanism
W
R
Write register
Read register
Take-over with V-sync
in 20 MHz domain
V40
V36B
HS
Take-over with V-sync
in 40 MHz domain
Rrstyp
Reset register
after reading
Take-over with V-sync
in back-end 36.0 MHz domain
Handshake mechanism required
Micronas
Aug. 16, 2004; 6251-552-1DS
39
MICRONAS [ MICRONAS ]
