ADVANCE INFORMATION
VPC 323xD, VPC 324xD
FP Sub-
address
Function
Default
Name
h’47 –
h’4b
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
This register is updated when the scaler mode register is written.
0
0
SCW1_0 – 4
h’4c –
h’50
scaler2 window controls, see table
5 12-bit registers for control of the nonlinear scaling
This register is updated when the scaler mode register is written.
SCW2_0 – 4
h’52
brightness register
bit[7:0] luma brightness −128...127
ITU-R output format: 16
16 SCBRI
16 BR
CVBS output format: −4
bit[9:8] horizontal lowpass filter for Y/C
0
0
LPF2
0
1
2
3
bypass
filter 1
filter 2
filter 3
bit[10]
horizontal lowpass filter for highresolution chroma
0/1 bypass/filter enabled
CBW2
this register is updated when the scaler mode register is written
h’53
contrast register
48 SCCT
48 CT
bit[5:0] luma contrast 0..63
ITU-R output format: 48
bit[7:6] horizontal peaking filter
0
1
2
broad
med
narrow
0
PFS
bit[10:8] peaking gain
0
no peaking... 7 max. peaking
0
0
PK
bit[10]
peaking filter coring enable
0/1 bypass/coring enabled
PKCOR
this register is updated when the scaler mode register is written
LLC Control Register
h’65
h’66
vertical freeze start
freeze llc pll for llc_start < line number < llc_stop
–10 LLC_START
bit[11:0]
allowed values from –156...+156
vertical freeze stop
4
LLC_STOP
freeze llc pll for llc_start < line number < llc_stop
bit[11:0]
allowed values from –156...+156
h’69
h’6a
42 = h’02A
2731 = h’AAB
20 bit llc clock center frequency
12.27 MHz −79437 = h’FEC9B2
LLC_CLOCKH
LLC_CLOCKL
13.5 MHz 174763 = h’02AAAB
14.75 MHz 194181 = h’02F685
16 MHz
18 MHz
–135927 = h’FDED08
174763 = h’02AAAB
Micronas
45
MICRONAS [ MICRONAS ]
