VPC 323xD, VPC 324xD
ADVANCE INFORMATION
FP Sub-
address
Function
Default
Name
Scaler Control Register
h’40
scaler mode register
bit[1:0] scaler mode
0
SCMODE
PANO
0
1
2
3
linear scaling mode
nonlinear scaling mode, ’panorama’
nonlinear scaling mode, ’waterglass’
reserved
bit[2]
bit[3]
reserved, set to 0
color mode select
0/1 4:2:2 mode / 4:1:1 mode
scaler bypass
reserved, set to 0
luma output format
S411
BYE
YOF
bit[4]
bit[5]
bit[6]
0
1
ITU-R luma output format (16–240)
CVBS output format
bit[7]
chroma output format
COF
0/1 ITU-R (offset binary) / signed
bit[10:8] reserved, set to 0
bit[11]
0
scaler update command, when the registers are
updated the bit is set to 1
h’41
pip control register
0
SCPIP
bit[1:0] horizontal downsampling
DOWNSAMP
0
1
2
3
no downsampling
downsampling by 2
downsampling by 4
downsampling by 8
bit[3:2] vertical compression for PIP
PIPSIZE
0
1
2
3
compression by 2
compression by 3
compression by 4
compression by 6
bit[4]
bit[5]
vertical filter enable
interlace offset for vertical filter (NTSC mode only)
PIPE
INTERLACE_OFF
0
1
start in line 283 of 2nd field (ITUR 656 spec)
start in line 282 of 2nd field (NTSC spec)
this register is updated when the scaler mode register is written
h’42
active video length for 1H-FIFO
bit[11:0] length in pixels
1080 FFLIM
D3000 mode (1296/h)1080
LLC mode (864/h)720
this register is updated when the scaler mode register is written
h’43
h’44
h’45
scaler1 coefficient: This scaler compresses the signal.
For compression by a factor c, the value c*1024 is required.
1024 SCINC1
1024 SCINC2
bit[11:0]
allowed values from 1024... 4095
This register is updated when the scaler mode register is written.
scaler2 coefficient: This scaler expands the signal.
For expansion by a factor c, the value 1/c*1024 is required.
bit[11:0]
allowed values from 256..1024
This register is updated when the scaler mode register is written.
scaler1/2 nonlinear scaling coefficient
0
SCINC
This register is updated when the scaler mode register is written.
44
Micronas
MICRONAS [ MICRONAS ]
