ADVANCE INFORMATION
VDP 313xY
3.5. Pin Circuits
VSUPAF
VSUPD
To ADC
GNDAF
GNDD
Fig. 3–8: Input pins CIN1,CIN2
Fig. 3–3: Input pin TEST, RESQ
VSUPAF
P
VINx
–
+
N
GNDD
N
VREF
Fig. 3–4: Input/Output pins SDA, SCL
GNDAF
Fig. 3–9: Output pin VOUT
P
VSUPD
P
XTAL2
XTAL1
VSUPAF
P
N
–
P
+
fXTAL
VRT
ADC Reference
N
N
=
VREF
GNDD
SGND
Fig. 3–10: Supply pins VRT, SGND
Fig. 3–5: Input/Output pins XTAL1, XTAL2
VSUPD
N
P
P
Clamping
N
GNDAB
N
N
Fig. 3–11: Input pins RIN, GIN, BIN
GNDD
Fig. 3–6: Output pin CLK20
N
VSUPAF
To ADC
Bias
N
GNDAB
Fig. 3–12: Output pins ROUT, GOUT, BOUT,
SVMOUT
GNDAF
Fig. 3–7: Input pins VIN1–VIN4, CBIN, CRIN
Micronas
57
MICRONAS [ MICRONAS ]
