欢迎访问ic37.com |
会员登录 免费注册
发布采购

VDP3130Y 参数 Datasheet PDF下载

VDP3130Y图片预览
型号: VDP3130Y
PDF下载: 下载PDF文件 查看货源
内容描述: 视频处理器家族 [Video Processor Family]
分类和应用:
文件页数/大小: 76 页 / 1707 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号VDP3130Y的Datasheet PDF文件第52页浏览型号VDP3130Y的Datasheet PDF文件第53页浏览型号VDP3130Y的Datasheet PDF文件第54页浏览型号VDP3130Y的Datasheet PDF文件第55页浏览型号VDP3130Y的Datasheet PDF文件第57页浏览型号VDP3130Y的Datasheet PDF文件第58页浏览型号VDP3130Y的Datasheet PDF文件第59页浏览型号VDP3130Y的Datasheet PDF文件第60页  
VDP 313xY  
ADVANCE INFORMATION  
Pin 37, 38, 39 Analog RGB Outputs, ROUT, GOUT,  
BOUT (Fig. 312)  
This are the analog Red/Green/Blue outputs of the  
backend. The outputs sink a current of max. 8 mA.  
Pin 57 Reference Voltage Top, VRT (Fig. 310)  
Via this pin, the reference voltage for the A/D convert-  
ers is decoupled. The pin is connected with 10 µF/  
47 nF to the Signal Ground Pin.  
Pin 40 DAC Reference Decoupling, VRD (Fig. 320)  
Via this pin the DAC reference voltage is decoupled by  
an external capacitance. The DAC output currents  
depend on this voltage, therefore a pull-down transis-  
tor can be used to shut off all beam currents. A decou-  
pling capacitor of 3.3 µF/100 nF is required.  
Pin 58 Supply Voltage (Analog Front-end), VSUPAF  
Pin 59 Analog Video Output, VOUT (Fig. 39)  
The analog video signal that is selected for the main  
(luma, cvbs) adc is output at this pin. An emitter fol-  
lower is required at this pin.  
Pin 41, 42, 43, 45, 46, 47 Analog RGB Inputs, RIN1/  
2, GIN1/2, BIN1/2 (Fig. 311)  
Pin 61...64 Analog Video Input 14, VIN14 (Fig. 3–  
7)  
These pins are used to insert an external analog RGB  
signal, e.g. from a SCART connector which can by  
switched to the analog RGB outputs with the fast blank  
signal. The analog backend provides separate bright-  
ness and contrast settings for the external analog RGB  
signals.  
These are the analog video inputs. A CVBS or S-VHS  
luma signal is converted using the luma (Video 1) AD  
converter. The input signal must be AC-coupled.  
3.4. Pin Configuration  
Pin 44, 48 Fast Blank Inputs, FBLIN1/2 (Fig. 315)  
These pins are used to switch the RGB outputs to the  
external analog RGB inputs.  
TEST  
RESQ  
SCL  
1
64 VIN4  
2
63 VIN3  
3
62 VIN2  
Pin 49 Main Clock Output, CLK20 ( Fig. 36)  
This is the 20.25 MHz main system clock, that is used  
by all circuits in a high-end VDP system. All external  
timing is derived from this clock.  
SDA  
4
61 VIN1  
GNDD  
HCS  
5
60 CIN1  
6
59 VOUT  
58 VSUPAF  
57 VRT  
FSY  
7
CSY  
8
Pin 50 Horizontal Drive Output, HOUT (Fig. 313)  
This open drain output supplies the the drive pulse for  
the horizontal output stage. The polarity and gating  
with the flyback pulse are selectable by software.  
VS  
9
56 SGND  
55 GNDAF  
54 CBIN  
53 CIN 2/CRIN  
52 XTAL 2  
51 XTAL 1  
50 HOUT  
49 CLK20  
48 FBLIN2  
47 BIN2  
INTLC  
VPROT  
SAFETY  
HFLB  
GNDD  
VSUPD  
GNDD  
VSUPD  
10  
11  
12  
13  
14  
15  
16  
17  
Pin 51, 52 Crystal Input and Output, XTAL1, XTAL2  
(Fig. 35)  
These pins are connected to an 20.25 MHz crystal  
oscillator is digitally tuned by integrated shunt capaci-  
tances. The Clk20 signal is derived from this oscillator.  
P0 18  
P1 19  
P2 20  
P3 21  
P4 22  
P5 23  
P6 24  
46 GIN2  
45 RIN2  
Pin 53, 54, 60Analog Chroma Inputs, CIN1, CIN2/  
CRIN, CBIN, (Fig. 37, Fig. 38)  
44 FBLIN  
43 BIN  
CIN1, CIN2 are the analog chroma inputs for S-VHS. A  
S-VHS chroma signal is converted using the chroma  
(Video2) AD converter. A resistive devider is used to  
BIAS the inout signal to middle of converter range. The  
input signal must be AC coupled. Together with the  
CBIN pin CIN2 can alternatively be used as chroma  
component input for the analog YCRCB interface.  
42 GIN  
41 RIN  
GNDD  
25  
26  
27  
28  
29  
30  
31  
40 VRD  
RSW2  
RSW1  
SENSE  
GNDM  
VERTQ  
VERT  
39 BOUT  
38 GOUT  
37 ROUT  
36 VSUPAB  
35 GNDAB  
34 SVMOUT  
33 XREF  
Pin 55 Ground (Analog Front-end), GNDAF  
Pin 56 Ground (Analog Signal Input),  
SGND (Fig. 310)  
E/W 32  
This is the high quality ground reference for the video  
input signals.  
Fig. 32:64-pin PSDIP package  
56  
Micronas