VDP 313xY
ADVANCE INFORMATION
2.14.2.Control and Status Registers
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 2–4.
Table 2–4 gives definitions of the VDP control and sta-
tus registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read opera-
tions. Write registers that can be read back are indi-
cated in Table 2–4.
The register modes given in Table 2–4 are
– w: write only register
– w/r:write/read data register
– r: read data from VPC
– v: register is latched with vertical sync
– h: register is latched with horizontal sync
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 2–6.
Table 2–4: I2C control and status registers of the video frontend
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
FP Interface
35
8
r
FP status
bit[0]
FPSTA
write request
read request
busy
bit[1]
bit[2]
36
37
38
16
16
16
w
bit[8:0]
9-bit FP read address
reserved, set to zero
FPRD
FPWR
FPDAT
bit[11:9]
w
bit[8:0]
9-bit FP write address
reserved, set to zero
bit[11:9]
w/r
bit[11:0]
FP data register,
reading/writing to this register will
autoincrement the FP read/write
address.
Only 16 bit of data are transferred
per I2C teleramm.
Black Line Detector
12 16
r
read only register, do not write to this register!
after reading, LOWLIN and UPLIN are reset to 127 to
start a new measurement
−
BLKLIN
LOWLIN
bit[6:0]
bit[7]
number of lower black lines
always 0
UPLIN
bit[14:8]
bit[15]
number of upper black lines
normal/black picture
BLKPIC
30
Micronas
MICRONAS [ MICRONAS ]
