VDP 313xY
ADVANCE INFORMATION
2.12.Synchronization and Deflection
extracted in the front-end, are implemented in hard-
ware in the back-end.
The synchronization and deflection processing is dis-
tributed over front-end and back-end. The video
clamping, horizontal and vertical sync separation and
all video related timing information are processed in
the front-end. Most of the processing that runs at the
horizontal frequency is programmed on the internal
Fast Processor (FP). Also the values for vertical and
East/West deflection are calculated by the FP soft-
ware.
2.12.1. Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–24). This block
contains two phase-locked loops:
– PLL2 generates the horizontal and vertical timing,
e.g. blanking, clamping and composite sync. Phase
and frequency are synchronized by the front sync
signal.
The information extracted by the video sync process-
ing is multiplexed onto the hardware front sync signal
(FSY) and distributed internally to the rest of the video
processing system.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal out-
put stage. Phase and frequency are synchronized
by the oscillator signal of PLL2.
The data for the vertical deflection, the sawtooth and
the East/West correction signal is calculated in the
front end. The data is transferred to the back-end by a
single wire interface.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for
the drive pulse. The generator runs at 1 MHz; in the
output stage the frequency is divided down to give
drive-pulse period and width. The horizontal drive
uses an open drain output transistor.
The display related synchronization, i.e. generation of
horizontal and vertical drive and synchronization of
horizontal and vertical drive to the video timing
HFLB
PLL3
1:64
DAC
skew
phase
comparator
&
sinewave
generator
&
measure-
DCO
&
HOUT
output
ment
LPF
stage
lowpass
angle &
bow
+
blanking, clamping, etc.
main
sync
display
timing
PLL2
MSY
FSY
CSY
VS
INTLC
generator
sync
generation
phase
front
sync
interface
line
counter
comparator
DCO
&
lowpass
vertical reset
clock & control
VPROT
EW
PWM
E/W
15 bit
correction
vertical
serial
data
VDATA
VERT
PWM
15 bit
sawtooth
VERTQ
Fig. 2–24: Deflection processing block diagram
26
Micronas
MICRONAS [ MICRONAS ]
