ADVANCE INFORMATION
VDP 313xY
Table 2–4: I2C control and status registers of the video frontend
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
Miscellaneous
29 16
w/r
Test pattern generator:
TPG
bit[10:0]
bit[11]
reserved (set to 0)
0
0
TPGEN
TPGMODE
0/1
disable/enable test
pattern generator
bit[13:12]
output mode:
Y/C = ramp (240 ... 17)
Y/C = 16
Y/C = 90
Y/C = 240
0
00
01
10
11
bit[15:14] 0/1
reserved (set to 0)
0
22
16
w/r
NEWLINE
NEWLIN
(available for versions with panorama scaler only):
bit[10:0]
NEWLINE register
50
This register defines the readout
start of the next line in respect to
the value of the sync counter.
Value of this register must be
greater than 31 for correct
operation.
bit[15:11]
reserved (set to 0)
Micronas
31
MICRONAS [ MICRONAS ]
