VCT 38xxA
ADVANCE INFORMATION
S
S
S
S
S
S
0010001
0010001
0010001
0010001
0010001
0010001
W
W
W
W
W
W
Ack
Ack
Ack
Ack
Ack
Ack
0111 1000
0111 1001
0111 1010
0111 1011
0111 1100
0111 1100
Ack
Ack
Ack
Ack
Ack
Ack
n Byte Sub 1
n Byte Sub 2
n Byte Sub 3
n Byte Sub 4
n Byte Data
0010001
Ack
Ack
Ack
Ack
Ack
R
P
P
P
P
P
S
S
Ack
Ack
last Byte Data Nak
n−1 Byte Data
P
P
S
0010001
W
Ack
0111 1101
Ack
0010001
R
Ack
Status
Status
Ack
Nak
W
R
Ack
Nak
S
=
=
=
=
=
=
=
=
0
1
0
1
1
0
SDA
SCL
S
P
Start
Stop
Interrupt
P
Data from TPU
Fig. 3–21: I2C bus protocol
3.14.1.5. Hardware Identification
A separate I2C bus slave register is reserved to read
out the hardware version of VCT 38xxA. This register
is active in standby mode.
2
I C Sub
address
Number
of bits
Mode
Function
Default Name
h’9F
16
r
Hardware version number
read HWID
only TC
PROD
bit[7:0]
hardware id (A3=h’13, B1=h’21 a.s.o.)
product code VCT38xy (VCT3832=h’32)
bit[15:8]
84
Micronas
MICRONAS [ MICRONAS ]
